Distributed pin diode phase shifter

• US 4,675,628 A
• Filed: 02/28/1985
• Issued: 06/23/1987
• Est. Priority Date: 02/28/1985
• Status: Expired due to Fees

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: RCA Corporation
• Inventors: Rosen, Arye
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): LEE, BENNY T
• Application Number:
  US06/706,752
• Time in Patent Office: 845 Days
• Field of Search: 333/164, 333/161, 333/156, 357/58, 307/317 R
• US Class Current: 333/164
• CPC Class Codes: H01P 1/185 using a diode or a gas filled discharge tube

Abstract

A monolithic chip phase shifter consists of a PIN diode which is laterally elongated and shaped into a microstrip-like transmission line. The transmission line has characteristics determined in part by the capacitances associated with the intrinsic layer of the diode. Alternating-current (AC) signals are coupled through the transmission line. Direct-voltage reverse bias, no bias or direct-current forward bias are applied to select the appropriate value of equivalent shunt capacitance of the transmission line to provide the desired phase shift of the AC signals passing therethrough. A high-impedance coupling device couples the bias to the transmission line to prevent leakage of signal to the bias source.

Claims

1. A phase shifter comprising:

a monolithic chip including a pair of mutually parallel substantially flat sides, said chip comprising doping layers oriented parallel with and in between said substantially flat sides and defining a PIN junction including a P doping layer and an N doping layer separated by a substantially intrinsic layer, said PIN junction being elongated along a line parallel with said substantially flat sides to define first and second ends of said PIN junction;

applying means coupled to said P doping layer and to said N doping layer of said PIN junction at said first end and adapted to be coupled to a source of alternating current signal, said source of alternating current signal including a first and second terminals, for applying said first terminal to said P doping layer and applying said second terminal to said N doping layer at said first end of said PIN junction whereby said alternating current signal propagates from said first end towards said second end through said PIN junction;

alternating current coupling means coupled to said P doping layer and to said N doping layer of said PIN junction at said second end and adapted to be coupled to an alternating current utilization means, said alternating current utilization means including first and second terminals, for coupling said first terminal of said alternating current utilization means to said P doping layer and said second terminal of said alternating current utilization means to said N doping layer, thereby coupling alternating current signal from said second end; and

bias means coupled to said P doping layer and to said N doping layer of said PIN junction for applying a direct bias to said PIN junction for biasing said junction into one of first and second states, said first state being forward bias in which said P doping layer is at a positive voltage with respect to said N doping layer, and said second state being reverse bias in which said P doping layer is at a negative voltage with respect to said N doping layer for controlling the phase of said signal coupled from said second end of said PIN junction in a continuous manner in response to the magnitude of said bias.

2. A PIN diode distributed phase shifter, comprising:

a substantially flat monolithic chip including a first layer comprising one of n+ and p+ doped semiconductor overlaid by a substantially intrinsic semiconductor layer, and also including a first elongated strip comprising the other one of said n+ and p+ doped semiconductor overlying said intrinsic semiconductor layer, said elongated strip having first and second ends and a traverse dimension orthogonal to the direction of elongation of said elongated strip, the layers forming an elongated PIN junction;

a first metallization layer bonded over substantially the entire first layer on a side remote from said intrinsic semiconductor layer;

a second metallization layer bonded over substantially the entire elongated strip on a side remote from said intrinsic semiconductor layer, thereby forming in conjunction with said first metallization layer and said intrinsic semiconductor layer a transmission line having a shunt capacitance associated with said PIN junction;

coupling means for coupling an alternating signal to said first end of said strip for forming a signal propagating principally in said PIN junction toward said second end of said strip, and means for coupling a phase shifted alternating signal from said second end of said strip to utilization means; and

control means coupled to said first and second metallization layers for applying a direct bias to said second metallization layer relative to said first metallization layer for selectively establishing one of first and second bias conditions for said PIN junction, said first bias condition being forward-bias and said second bias condition being reverse-bias whereby the phase of said phase shifted alternating signal is thereby shifted relative to an unbiased condition of said PIN junction in a substantially continuous manner in response to the magnitude of said direct bias.

3. A phase shifter according to claim 2, wherein said control means comprises a high impedance means coupled to said second metallization layer at a point between said first and second ends for simultaneously coupling said bias to said second metallization layer and preventing substantial leakage of said alternating signal away from said transmission line.

4. A phase shifter according to claim 3 wherein said high impedance means comprises a choke.

5. A phase shifter according to claim 2 wherein said control means comprises a controllable source of direct current coupled to said first and second metallization layers for forward biasing said junction with a forward current.

6. A phase shifter according to claim 2 wherein said control means comprises a controllable source of direct voltage coupled to said first and second metallization layers for reverse-biasing said junction.

7. A PIN diode distributed phase shifter, comprising:

a substantially flat monolithic chip including a first semiconductor layer comprising one of n+ and p+ doped semiconductor overlaid by a substantially intrinsic semiconductor layer, and also including a first elongated strip comprising the other one of said n+ and p+ doped semiconductor overlying said intrinsic semiconductor layer, said elongated strip having first and second ends and a transverse dimension orthogonal to the direction of elongation of said elongated strip, the layers forming an elongated PIN junction;

a first metallization layer bonded over substantially the entirety of said first semiconductor layer on a side remote from said intrinsic semiconductor layer;

a second metallization layer bonded over substantially the entirety of said elongated strip on a side remote from said intrinsic semiconductor layer, thereby forming in conjunction with said first metallization layer and said intrinsic semiconductor layer a transmission line having shunt capacitance associated with said PIN junction;

coupling means for coupling an alternating signal to said first end of said strip for forming a signal propagating principally in said PIN junction towards said second end of said strip, and means for coupling a phase shifted alternating signal from said second end of said strip to utilization means; and

control means coupled to said first and second metallization layers and comprising a solenoidally wound choke, having high impedance, coupled to said second metallization layer for applying a direct bias to said second metallization layer relative to said first metallization layer for selectively establishing one of first and second bias conditions for said PIN junction, said first bias condition being forward-bias and said second bias condition being reverse-bias, whereby the phase of said phase shifted alternating signal is thereby shifted relative to an unbiased condition of said PIN junction in a substantially continuous manner in response to the magnitude of said direct bias.

8. A phase shifter according to claim 7 wherein said choke comprises a magnetic core.

9. A PIN diode distributed phase shifter, comprising:

a substantially flat monolithic chip including an n+ semiconductive layer overlaid by a substantially intrinsic semiconductor layer, and also including a p+ semiconductive layer in the form of an elongated strip overlying said intrinsic semiconductive layer, said elongated strip having first and second ends, the layers forming an elongated PIN junction;

a first metallization layer bonded over substantially the entire side of said n+ semiconductive layer remote from said intrinsic semiconductive layer;

a second metallization layer bonded over substantially the entire side of said strip remote from said intrinsic semiconductive layer thereby forming in conjunction with said first metallization layer a transmission line having a series inductance associated principally with said second metallization layer and a shunt capacitance associated with said PIN junction;

coupling means for coupling an alternating signal to said first end of said strip for forming a signal propagating principally in said PIN junction toward said second end of said strip, and means for coupling a phase shifted alternating signal from said second end of said strip to utilization means; and

control means coupled across said first and second metallization layers for applying a direct bias to said second metallization layer relative to said first metallization layer for selectively establishing one of first and second bias conditions for said PIN junction, said first bias condition being forward-bias and said second bias condition being reverse-bias for controlling the phase of said phase shifted alternating signal in response to the magnitude of said direct bias.

10. A phase-shifter according to claim 9, wherein said control means comprises high impedance means coupled to said second metallization layer at a point between said first and second ends for simultaneously coupling said bias to said second metallization layer and preventing substantial leakage of said alternating signal away from said transmission line.

11. A phase shifter according to claim 10 wherein said high impedance means comprises a choke.

12. A phase shifter according to claim 11 wherein said choke comprises a solenoid winding.

13. A PIN diode distributed phase shifter, comprising:

a substantially flat monolithic chip including an n+ semiconductive layer overlaid by a substantially intrinsic semiconductive layer, and also including a p+ semiconductive layer in the form of an elongated first strip overlying said intrinsic semiconductive layer and having a transverse dimension orthogonal to the direction of elongation, said elongated first strip having first and second ends, the layers forming an elongated PIN junction;

a first metallization layer bonded over substantially the entire side of said n+ semiconductive layer remote from said intrinsic semiconductive layer;

a second metallization layer bonded over substantially the entire side of said first strip remote from said intrinsic semiconductive layer thereby forming in conjunction with said first metallization layer a transmission line having a shunt capacitance associated principally with said PIN junction;

coupling means for cupling an alternating signal to said first end of said strip for forming a signal propagating principally in said PIN junction toward said second end of said first strip, and means for coupling a phase shifted alternating signal from said second end of said first strip to utilization means; and

control means coupled to said first and second metallization layers and comprising a second elongated strip having a transverse dimension orthogonal to the direction of elongation which is narrower than said first strip transverse dimension, of p+ layer overlying said intrinsic layer and intersecting said first elongated strip of p+ layer, and a third metallization layer overlying said second strip and intersecting said second metallization layer, for applying a direct bias to said second metallization layer relative to said first metallization layer for selectively establishing one of first and second bias conditions for said PIN junction, said first bias condition being forward-bias and said second bias condition being reverse-bias for controlling the phase of said phase shifted alterating signal in response to the magnitude of said direct bias.

14. A phase shifter according to claim 13 wherein the length of said second elongated strip is approximately one quarter wavelength at the design center.

15. A phase shifter according to claim 14 further comprising low impedance means coupled to the end of said elongated second strip remote from the intersection of said elongated second strip with said first elongated strip.

16. A PIN diode distributed phase shifter, comprising:

a substantially flat monolithic chip including a first layer comprising one of n+ and p+ doped semiconductor overlaid by a substantially intrinsic semiconductor layer, and also including a first elongated strip comprising the other one of said n+ and p+ doped semiconductor overlying said intrinsic semiconductor layer, said elongated strip having first and second ends and a transverse dimension orthogonal to the direction of elongation of said elongated strip, the layers forming an elongated PIN junction;

a first metallization layer bonded over substantially the entire side of said first layer remote from said intrinsic semiconductor layer;

a second metallization layer bonded over substantially the entire elongated strip on a side remote from said intrinsic semiconductor layer, thereby forming in conjunction with said first metallization layer and said intrinsicl semiconductor layer a transmission line having a shunt capacitance associated with said PIN junction;

coupling means for coupling an alternating signal to said first end of said strip for forming a signal propagating principally in said PIN junction toward said second end of said strip, and means for coupling a phase shifted alternating signal from said second end of said strip to utilization means; and

control means coupled to said first and second metallization layers and comprising a second elongated strip including first and second ends, comprising said other one of said n+ and p+ doped semiconductor overlying said intrinsic layer, said second elongated strip having a transverse dimension orthogonal to the direction of elongation of said second elongated strip which is narrower than said transverse dimension of said first elongated strip, said first end of said second elongated strip intersecting said first elongated strip at a first intersection and merging with said first elongated strip at said first intersection, and a third metallization layer overlying said second elongated strip and intersecting said second metallization layer at a second intersection overlying said first intersection, said third metallization layer merging with said second metallization layer at said second intersection to form a high impedance choke for applying a direct bias from said second end of said second elongated strip to said second metallization layer relative to said first metallization layer for selectively establishing one of first and second bias conditions for said PIN junction, said first bias condition being forward-bias and said second bias condition being reverse-bias whereby the phase of said phase shifted signal is thereby shifted relative to an unbiased condition of said PIN junction in a substantially continuous manner in response to the magnitude of said direct bias.

17. A phase shifter according to claim 16 wherein the length of said second elongated strip is approximately one quarter wavelength at the design center frequency.

18. A phase shifter according to claim 17 further comprising low impedance means coupled to the end of said second elongated strip remote from the first intersection of said second elongated strip with said first elongated strip.