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Inertial reference system

  • US 4,675,820 A
  • Filed: 06/14/1984
  • Issued: 06/23/1987
  • Est. Priority Date: 06/14/1984
  • Status: Expired due to Fees
First Claim
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1. An inertial reference system comprising:

  • an inertial sensor assembly including;

    (a) first, second and third ring laser gyros respectfully mounted for sensing angular deviation of said inertial sensor assembly about the X, Y and Z axes of an orthogonal coordinate system, said first ring laser gyro including means for producing first and second signals +Δ

    θ

    x and -Δ

    θ

    x, having pulse repetition rates that are respectively proportional to the rate of clockwise and counterclockwise rotation of said first ring laser gyro about said X axis, said second ring laser gyro including means for producing third and fourth signals, +Δ

    θ

    y and -Δ

    θ

    y, having pulse repetition rates that are respectively proportional to the rate of clockwise and counterclockwise angular displacement of said second ring laser gyro about said Y axis, said third ring laser gyro including means for producing fifth and sixth signals, +Δ

    θ

    z and -Δ

    θ

    z, having pulse repetition rates that are respectively proportional to the rate of clockwise and counterclockwise angular displacement of said third ring laser gyro about said Z axis;

    (b) accelerometer means for producing output signals Δ

    Vx, Δ

    Vy and Δ

    Vz representative of the change in velocity of the inertial sensor assembly in said coordinate axes X, Y and Z, respectively;

    dither means for cyclically and asynchronously dithering each of said first, second and third ring laser gyros;

    a first processor, P1, for predeterminedly accessing and processing said first, second, third, fourth, fifth and sixth signals supplied by said first, second and third ring laser gyros and said Δ

    Vx, Δ

    Vy and Δ

    Vz signals supplied by said accelerometer means, said P1 processor including;

    (a) gyro counter means for accumulating over each dither cycle of said cyclically, asynchronous, dithering of said first, second and third ring laser gyros, said first, third and fifth signals +Δ

    θ

    x, +Δ

    θ

    y and +Δ

    θ

    z supplied by said first, second and third ring laser gyros and for accumulating over each said dither cycle of said cyclically, asynchronous dithering of said first, second and third ring laser gyros, said second, fourth and sixth signals -Δ

    θ

    x, -Δ

    θ

    y and -Δ

    θ

    z supplied by said first, second and third ring laser gyros;

    (b) gyro storage means for storing said accumulated pulse counts for each of said signals +Δ

    θ

    x, +Δ

    θ

    y, +Δ

    θ

    z, -Δ

    θ

    x, -Δ

    θ

    y and -Δ

    θ

    z ;

    (c) logic means for periodically sampling said gyro storage means and predeterminedly processing said stored pulse counts for producing a seventh signal, Δ

    θ

    x, representative of the angular rate of said first ring laser gyro, an eighth signal, Δ

    θ

    y, representative of the angular rate of said second ring laser gyro, and a ninth signal, Δ

    θ

    z, representative of the angular rate of said third ring laser gyro, each said signal Δ

    θ

    x, Δ

    θ

    y and Δ

    θ

    z being synchronized to a common interval, said logic means including means for resynchronizing each stored pulse count to each logic means sampling time;

    (d) means for coning correction for said Δ

    θ

    x, Δ

    θ

    y and Δ

    θ

    z signals;

    (e) means for sculling correction for said Δ

    Vx, Δ

    Vy and Δ

    Vz signals;

    (f) means for temperature compensating said Δ

    θ

    x, Δ

    θ

    y, Δ

    θ

    z, Δ

    Vx, Δ

    Vy and Δ

    Vz signals; and

    means for supplying signals that are representative of said temperature, sculling and coning compensated signals; and

    ,a second processor, P2, for performing navigational computations with the temperature, sculling and coning compensated signals supplied by said P1 processor.

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