Apparatus for the display and storage of television picture information by using a memory accessible from a computer

• US 4,675,842 A
• Filed: 11/06/1984
• Issued: 06/23/1987
• Est. Priority Date: 05/07/1980
• Status: Expired due to Fees

• Current Assignee: Szamitastechnikai Koordinacios Intezet
• Original Assignee: Szamitastechnikai Koordinacios Intezet
• Inventors: Szenes, Zsursa, Endrodi, Bela
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): Clark, David L.
• Application Number:
  US06/669,040
• Time in Patent Office: 959 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/518, 340/750, 340/814
• US Class Current: 711/207
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor

Abstract

An apparatus for the display and storage of television picture information by using a dynamic random access memory accessible from a computer. The apparatus includes an interface providing connection to the computer, an address modifying circuit, an address switching unit including a first input group connected to predetermined address lines of the address bus of the address generator and a second group connected to predetermined address lines of the interface, and a parallel to series converter. The inputs of the address modifying circuit being coupled to the output of the address switching unit to provide modified addresses for the memory when any of the input groups addresses the memory. The control inputs of the address switching unit and of the data switching unit are connected to a horizontal address line of the address bus associated with a horizontal address bit (X₃) of low significance. The memory includes matrices whose rows are to be accessed by row addresses for reading or writing within a time period less than that required for refreshment. The picture addresses are allocated among the row and column addresses of the matrices in such a way that the row addresses (X₄, X₅, X₆, X₇, Y₁, Y₂, Y_o) occur in a shorter period than that required for the refreshment. The horizontal address bit (X₃) of low significance allocating one of two sets of the matrices to the address generator and to the display and allocating the other set to the interface of the computer for reading and writing. The access cycles of the two sets occurring substantially at the same time.

Claims

1. An apparatus for the display and storage of television picture information by using a dynamic random access memory accessible from a computer, comprising a clock generator, an address generator coupled to the clock generator for generating horizontal and vertical picture addresses (X_o -X₉, Y_o -Y₉), a synchronizing unit connected to the address generator and providing line and picture synchronizing signals, an interface connected to the computer, a memory control unit, coupled to the address generator, the memory, and to the interface for controlling the memory, an address switching unit including a first input group connected to predetermined address lines of the address generator and a second input group connected to predetermined address lines of the interface, a pair of address modifying circuits with respective inputs coupled to a respective output group of the address switching unit and outputs coupled to address ports of the memory to provide modified addresses for the memory when any of the input groups addresses the memory, in which between the inputs and the outputs the following logical equations are true:

space="preserve" listing-type="equation">X.sub.8 =X'"'"'.sub.8 ;

X.sub.9 =X'"'"'.sub.9 ;

Y.sub.6 =Y'"'"'.sub.6 ;

Y.sub.7 =Y'"'"'.sub.7 if Y.sub.9 =0

and

space="preserve" listing-type="equation">1=X'"'"'.sub.8 ;

1=X'"'"'.sub.9 ;

X.sub.8 =Y'"'"'.sub.6 ;

X.sub.9 =Y'"'"'.sub.7 if Y.sub.9 =1,

in which addresses designated by X and Y represent states of corresponding horizontal and vertical bit lines of the address generator, addresses X'"'"' and Y'"'"' designate the states of the modified horizontal and vertical address lines at the output of the address modifying circuit, a data switching unit including a first and a second output group, the input of the data switching unit being connected to a data bus of the memory, a parallel to series converter with parallel ports coupled to the address generator and the first output group of the data switching unit and controlled by predetermined address lines of the address generator carrying the least significant horizontal address bits (X_o -X₂) to step the parallel data in sequence with least significant horizontal address bit (X_o) from or to the series port thereof, said series port connected to a digital to analog converter which converts and supplies said serially stepped bits as a video signal and to digital outputs of an analog to digital converter for transferring a digitized video signal from said analog to digital converter to the memory, the second output group of the data switching unit coupled to a data bus of said interface for transferring data between the memory and the interface, control inputs of the address switching unit and of the data switching unit being connected to horizontal address bit (X₃), said memory including matrices whose rows are to be accessed by row addresses for reading or writing within a time period less than that required for refresh of said memory, and said modified addresses specifying rows addressed by row and column addresses of the matrices such that the row addresses (X₄, X₅, X₆, X₇, Y₁, Y₂, Y_o) are updated in shorter consecutive periods than the time required for refresh of said memory, one of two sets of said matrices being addressed via a first one of said address modifying circuits by addresses generated from said address generator, the data lines of said set being coupled through said data switching unit with said converter, while the other set is addressed via the other one of said address modifying circuits by addresses generated from the computer and sent via said interface, the data lines of said other set coupled through said data switching unit with said interface, whereby the respective connections established to said sets through said switching units alternate according to the value of said control bit (X₃) alternating.

2. The apparatus as claimed in claim 1, wherein each set of the matrices includes a pair of groups of matrices, each group storing a respective half picture, a first one of said groups is enabled by the Y_o =1 condition, while the other one of said groups enabled by the Y_o =0 condition, in which Y_o represents the least significant vertical address bit.