×

Bus interface

  • US 4,675,865 A
  • Filed: 10/04/1985
  • Issued: 06/23/1987
  • Est. Priority Date: 10/04/1985
  • Status: Expired due to Fees
First Claim
Patent Images

1. An interface circuit for interfacing between a shared bus and a processor, both for extracting information, in the form of packets, from said bus and for transmitting information, in the form of packets, to said bus, said interface circuit comprising:

  • interface control means for receiving control information from said shared bus and transmitting control information to said shared bus in order to regulate accesses of said interface circuit to said shared bus independently of said processor;

    receiver means, responsive to control signals from said interface control means, for receiving data from said shared bus and for routing said data to a temporary data storage means;

    transmitter means, responsive to control signals from said interface control means, for transmitting data from said temporary data storage means to said shared bus; and

    access control means both for controlling the flow of data between said processor and said temporary data storage means and for regulating access to said storage means between said processor and said interface circuit.

View all claims
  • 2 Assignments
Timeline View
Assignment View
    ×
    ×