Circuit for controlling a receiver in an implanted device

• US 4,676,248 A
• Filed: 09/13/1985
• Issued: 06/30/1987
• Est. Priority Date: 04/30/1982
• Status: Expired due to Term

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Berntson, Peter K.
• Primary Examiner(s): Coven, Edward M.
• Application Number:
  US06/776,082
• Time in Patent Office: 655 Days
• Field of Search: 128/419 PG, 128/419 P, 128/903, 128/904, 128/423 R, 340/518, 340/825.1
• US Class Current: 607/59
• CPC Class Codes: A61N 1/37211 Means for communicating with stimulators
• CPC Class Codes: A61N 1/37252 Details of algorithms or data aspects of communication system, e.g. handshaking, transmitting specific data or segmenting data
• CPC Class Codes: H04B 1/202 by remote control

Abstract

A circuit for controlling a receiver in an implanted device and circuitry for decoding and storing received program signals is disclosed. In the circuit a control circuit periodically activates a receiver to surveil for remotely generating programming signals. When a program signal is detected by the receiver the control circuit latches the receiver into a continuously activated state for a predetermined time interval. If a reset code is detected from subsequently received signals the receiver is held in an activated condition for a further predetermined time interval. Decoding circuits including a timer are reset upon receipt of the refresh code and provide control over sequences of received programming data for use in programming the stimulation mode of output circuits in the implanted device.

Claims

1. Receiver apparatus for an implantable device of the remotely programmable type comprising:

an analog receiver operative when activated for receiving programming signals, including wakeup signals, from a remote programming unit;

digital circuit means for causing the receiver to be intermittently activated to watch for a remotely generated wake-up signal, said wake-up signal being of sufficient duration and period to coincide with an activated period of the receiver, the power consumption of said receiver being relatively higher when activated then when deactivated; and

digital latching means for causing the receiver to be continuously activated for a predetermined time interval when a wake-up signal is detected by the receiver while intermittently activated so that a series of programming signals may be received.

2. A circuit according to claim 1 wherein said means for causing the receiver to be continuously activated further includes reset means responsive to more than one programming signal detected by the receiver while continuously activated for causing said receiver to be continuously activated for at least one more predetermined time interval.

3. A circuit according to claim 2 wherein said intermittent activation is periodic and wherein the periodic rate is greater than one millisecond and the duty cycle of intermittent activation is less than one-hundred microseconds.

4. Receiver apparatus for an implantable device of the remotely programmable type comprising:

an analog receiver operative when activated for receiving programming signals from a remote programming unit;

digital circuit means for recurringly activating the receiver at a low duty cycle so that the receiver intermittently surveys for remotely generated programming signals, the power consumption of said receiver being relatively higher when activated than when deactivated;

digital latching means connected to the receiver and responsive to the first programming signal detected by the receiver for holding the receiver in an activated condition for a predetermined time interval; and

digital reset means responsive to more than one programming signal comprising a reset code detected by the receiver while held in said activated condition for causing said latching means to hold the receiver in an activated condition for another predetermined time interval.

5. A circuit according to claim 4 wherein said reset means includes a shift register for holding said more than one programming signal which comprises said reset code and selectively activated decode logic connected thereto for determining the presence of said reset code in the shift register.

6. A circuit according to claim 5 wherein said reset means includes a bit counter for activating said decode logic when a predetermined program signal count is reached.

7. A circuit according to claim 4 wherein said latching means includes a timer started by said first signal for timing said predetermined time interval.

8. A circuit for controlling the reception and decoding of remotely generated signals in an implantable device of the programmable type, comprising:

an analog receiver operative when activated for receiving programming signals from a remote programming unit;

digital circuit means for recurringly activating the receiver at a low duty cycle so that the receiver intermittently surveys for remotely generated programming signals, the power consumption of said receiver being relatively higher when activated than when deactivated;

digital latching means connected to the receiver and responsive to the first programming signal detected by the receiver for holding the receiver in an activated condition for a first predetermined time interval;

digital counting means for counting programming signals detected by the receiver;

digital reset means connected to said counting means and responsive to more than one programming signal comprising a reset code detected by the receiver while held in said activated condition for causing said latching means to hold the receiver in an activated condition for another first predetermined time interval and for resetting said counting means;

a programmable output circuit;

digital circuit means for linking a sequence of programming signals to the output circuit when a predetermined signal count is accumulated by said counting means; and

digital sequence timing means for causing said counting means to reset at the end of a second predetermined time interval beginning when said counting means is reset, said second time interval having a duration relative to the duration of a valid programming sequence so that programming sequences not completed within said second predetermined time interval are prevented from linking to the output circuit.

9. A circuit according to claim 8 wherein said latching means includes a timer started by said first signal for timing said first predetermined time interval.

10. A circuit according to claim 9 wherein said latching means includes a flip-flop set by said first signal and reset by said timer at the end of said first predetermined time interval.

11. A circuit according to claim 8 wherein said reset means includes a shift register for holding said more than one programming signal which comprises said reset code and decode logic connected thereto for determining the presence of said reset code in the shift register.

12. A circuit according to claim 11 wherein said decode logic is activated by said counting means when a predetermined program signal count is reached.