Passivated deep p/n junction

• US 4,676,845 A
• Filed: 02/18/1986
• Issued: 06/30/1987
• Est. Priority Date: 02/18/1986
• Status: Expired due to Fees

• Current Assignee: Spire Corporation Patriots Park
• Original Assignee: Spire Corporation
• Inventors: Spitzer, Mark B.
• Primary Examiner(s): Weisstuch, Aaron
• Application Number:
  US06/829,947
• Time in Patent Office: 497 Days
• Field of Search: 148/1.5, 148/176, 148/33, 148/33.3, 136/255, 136/261, 357/30, 357/91
• US Class Current: 148/33.3
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 31/02167 for solar cells
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10S 438/958 Passivation layer

Abstract

A passivated deep p/n junction obtained by ion implantation is disclosed. The passivated deep p/n junction is formed in a wafer, preferably a silicon wafer, thus providing an emitter region that is both lightly doped and extending to a depth of about one micrometer. The emitter region in turn is provided with a surface layer so as to reduce surface recombination. Preferably, the surface layer is a silicon oxide layer of about 0.01 micrometer thickness. The p/n junction is obtained by ion implantation whereby the dopant is introduced at room temperature and then distributed thermally. The surface layer preferably is formed near the end of the thermal distribution by admitting a small amount of dry oxygen to a gas stream, and passing the gas stream along the surface of the wafer.

Claims

1. A semiconductor wafer with a passivated deep p/n junction obtained by ion implantation, comprising the steps of:

(a) providing a semiconductor wafer;

(b) forming a lightly doped emitter region by ion implantation of a dopant material in one surface of said wafer to a depth of about one micrometer;

(c) thermally distributing said ion implanted dopant material to form said deep p/n junction; and

(d) passivating said deep p/n junction by forming a surface layer on said emitter region;

said lightly doped emitter region having a dopant concentration of no more than about 10¹⁹ cm^-3 ; and

said ion implantation of said dopant material being effected at room temperature and within an energy range of between 5 keV and 50 keV and with a dose of about 10¹⁵ ions per cm².

2. The wafer with a passivated deep p/n junction of claim 1 wherein said wafer is a silicon wafer of a thickness from about 50 micrometers to about 500 micrometers, wherein said surface layer is formed of silicon dioxide, and wherein said surface layer is about 0.01 micrometer thick.

3. The wafer with a passivated deep p/n junction of claim 2 wherein said silicon dioxide surface layer is formed as an integral step of said thermal distribution step of said ion implanted dopant material by admitting dry oxygen to a gas stream and passing said gas stream and dry oxygen along the surface of said lightly doped emitter region.

4. The wafer with a passivated deep p/n junction of claim 1 wherein said thermal distribution of said ion implanted dopant material is effected at a temperature of at least about 750°

C., and wherein said thermal distribution of said ion implanted dopant material is effected over a time period of at least about fifteen minutes.

5. The wafer with a passivated deep p/n junction of claim 1 wherein said surface layer is formed as an integral step of said theremal distribution step of said ion implanted dopant material.