Programmable logic storage element for programmable logic devices

• US 4,677,318 A
• Filed: 04/12/1985
• Issued: 06/30/1987
• Est. Priority Date: 04/12/1985
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Veenstra, Kerry S.
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): HUDSPETH, DAVID R
• Application Number:
  US06/722,684
• Time in Patent Office: 809 Days
• Field of Search: 307/440, 307/445, 307/465, 364/716
• US Class Current: 326/40
• CPC Class Codes: H03K 19/17716 with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register H03K19/17712 takes precedence
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

A storage element for use in a logic array including a flip-flop device and a complex logic circuit interconnected in such a way that the output of the complex logic circuit is an input to the flip-flop. A Toggle Flip-Flop Control (TFFC) signal, an invert control (INV) signal, and a clock (CLK) signal are also inputs to the complex logic circuit. The output of the flip-flop connects to an output pad, an internal direct feedback line which is one of the means by which the flip-flop is connected to the comples logic circuit, and an external feedback bus which leads back to an associated AND-OR array. The inptu to the complex logic circuit is generated by the standard AND-OR array which is programmable to some degree.

Claims

1. In a programmable logic array device including a programmable AND array which responds to input data signals and develops predetermined product terms, an OR array responsive to the said product terms and operative to develop corresponding logic signals, and logic storage means for temporarily storing said logic signals and either outputting them to output terminals or returning them to said AND array, an improved logic storage means comprising:

flip-flop means having first terminal means for receiving a next state logic signal, second terminal means for receiving a clock signal, and output terminal means; and

control logic circuit means having third terminal means coupled to said output terminal means for receiving a feedback signal, fourth terminal means for receiving an invert control signal, fifth terminal means for receiving a toggle control signal, sixth terminal means connected to said first terminal means, and input terminal means for receiving logic signals from said OR array, said control logic circuit means being responsive to said feedback signal, said invert control signal and said toggle control signal, and operative to develop on said sixth terminal means a signal having a predetermined relationship to the logic signal input on said input terminal means, whereby said flip-flop means and said control logic circuit means may be selectively caused to emulate particular types of flip-flop means determined at least in part by said invert control signal and said toggle control signal.

2. In a programmable logic array device as recited in claim 1 wherein said flip-flop means is a D-type flip-flop and wherein said control logic circuit means includes a first exclusive-OR gate having one input connected to said fourth terminal means and another input connected to said input terminal means, a second exclusive-OR gate having one input coupled to the output of said first exclusive OR gate and another input coupled to said third terminal means, and a multiplexer having a first input coupled to said fifth terminal means, a second input coupled to the output of said first exclusive-OR gate, a third input coupled to the output of said second exclusive-OR gate and an output forming said sixth terminal means.

3. In a programmable logic array device as recited in claim 1 wherein said flip-flop means is a D-type flip-flop and wherein said control logic circuit means includes a NAND gate having one input coupled to said third terminal means and another input coupled to said fifth terminal means, an exclusive-NOR gate having one input coupled to the output of said NAND gate and another input coupled to said fourth terminal means, and an exclusive-OR gate having one input coupled to the output of said exclusive-NOR gate and another input coupled to said input terminal means, the output thereof forming said sixth terminal means.

4. In a programmable logic array device as recited in claim 1 wherein said logic storage means is a T-type flip-flop.

5. A programmable logic array device comprising:

programmable AND array means which responds to input data signals and develops predetermined product terms;

OR array means responsive to the said product terms and operative to develop corresponding logic signals, and

logic storage means for temporarily storing said logic signals and either outputting them to output terminals or returning them to said AND array, said logic storage means including;

flip-flop means having first terminal means for receiving a next state logic signal, second terminal means for receiving a clock signal, and output terminal means; and

control logic circuit means having third terminal means coupled to said output terminal means for receiving a feedback signal, fourth terminal means for receiving an invert control signal, fifth terminal means for receiving a toggle control signal, sixth terminal means connected to said first terminal means, and input terminal means for receiving logic signals from said OR array, said control logic circuit means being responsive to said feedback signal, said invert control signal and said toggle control signal, and operative to develop on said sixth terminal means a signal having a predetermined relationship to the logic signal input on said input terminal means, whereby said flip-flop means and said control logic circuit means may be selectively caused to emulate particular types of flip-flop means determined at least in part by said invert control signal and said toggle control signal.

6. A programmable logic array device as recited in claim 5 wherein said flip-flop means is a D-type flip-flop and wherein said control logic circuit means includes a first exclusive-OR gate having one input connected to said fourth terminal means and another input connected to said input terminal means, a second exclusive-OR gate having one input coupled to the output of said first exclusive OR gate and another input coupled to said third terminal means, and a multiplexer having a first input coupled to said fifth terminal means, a second input coupled to the output of said first exclusive-OR gate, a third input coupled to the output of said second exclusive-OR gate and an output forming said sixth terminal means.

7. A programmable logic array device as recited in claim 5 wherein said flip-flop means is a D-type flip-flop and wherein said control logic circuit means includes a NAND gate having one input coupled to said third terminal means and another input coupled to said fifth terminal means, an exclusive-NOR gate having one input coupled to the output of said NAND gate and another input coupled to said fourth terminal means, and an exclusive-OR gate having one input coupled to the output of said exclusive-NOR gate and another input coupled to said input terminal means, the output thereof forming said sixth terminal means.

8. A programmable logic array device as recited in claim 5 wherein said logic storage means is a T-type flip-flop.

9. In a programmable logic array device including a programmable AND array which responds to input data signals and develops corresponding product term signals, an OR array which is responsive to said product term signals and is operative to develop a corresponding SUMTERM signal at its output, and logic storage means for receiving and temporarily storing said SUMTERM signal and for presently outputting a present state logic signal Q having a predetermined logical relationship to a previously input SUMTERM signal, and for subsequently outputting a next state logic signal Q+, an improved logic storage means comprising:

flip-flop means having first terminal means for receiving a next state logic signal Q+, second terminal means for receiving a clock signal, and output terminal means for developing a present state output signal Q; and

programmable control circuit means responsive to said SUMTERM signal and said present state logic signal Q and operative to develop a next state logic signal Q+, in accordance with one of the following tables selected from the group consisting of

space="preserve" listing-type="tabular"> TABLE A______________________________________SUMTERM Q Q+______________________________________0 0 00 1 01 0 11 1 1,______________________________________

space="preserve" listing-type="tabular"> TABLE B______________________________________SUMTERM Q Q+______________________________________0 0 10 1 11 0 01 1 0,______________________________________

space="preserve" listing-type="tabular"> TABLE C______________________________________SUMTERM Q Q+______________________________________0 0 00 1 11 0 11 1 0, and______________________________________

space="preserve" listing-type="tabular"> TABLE D______________________________________SUMTERM Q Q+______________________________________0 0 10 1 01 0 01 1 1.______________________________________

10. In a programmable logic array device as recited in claim 9 wherein said programmable control circuit means includes an exclusive OR gate having a first input coupled to the output of said OR array, a second input coupled to said output terminal means, and an output coupled to said first terminal means.

11. In a programmable logic array device as recited in claim 10 wherein said second input is coupled to said output terminal means through at least one programmable logic device.

12. In a programmable logic array device as recited in claim 10 wherein said second input is coupled to said output terminal means through a first programmable logic device and a second programmable logic device.

13. In a programmable logic array device as recited in claim 12 wherein said first programmable logic device includes a NAND gate having one input coupled to said output terminal means, and another input for receiving a toggle control signal.

14. In a programmable logic array device as recited in claim 13 wherein said second programmable logic device includes an exclusive NOR gate having one input coupled to the output of said NAND gate, another input for receiving an invert control signal, and an output coupled to said second input of said exclusive OR gate.

15. In a programmable logic array device as recited in claim 9 wherein said programmable control circuit means includes:

a first exclusive OR gate having one input coupled to the output of said OR array, and another input for receiving an invert control signal;

a second exclusive OR gate having one input coupled to said output terminal, and another input coupled to the output of said first exclusive OR gate; and

a multiplexer means having a first input coupled to the output of said first exclusive OR gate, a second input coupled to the output of said second exclusive OR gate, a control input for receiving a toggle control signal, and an output coupled to said first terminal means.