Data communication system and method and communication controller and method therefor, having a data/clock synchronizer and method

• US 4,677,614 A
• Filed: 02/15/1983
• Issued: 06/30/1987
• Est. Priority Date: 02/15/1983
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: EMC Controls, Inc.
• Inventors: Circo, Miles M.
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/466,560
• Time in Patent Office: 1,596 Days
• Field of Search: 370/86, 370/100, 370/103, 370/85, 370/16, 370/89, 375/118, 375/119, 375/120, 375/107, 340/825.05
• US Class Current: 370/222
• CPC Class Codes: H04J 3/0641 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04L 12/422 Synchronisation for ring networks Time Division Multiplex ring networks, e.g. SDH/SONET H04J3/085
• CPC Class Codes: H04L 12/433 with asynchronous transmission, e.g. token ring, register insertion
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A communication system and method is provided, in which synchronous (i.e., clocked) serial digital data may be sent and received from any given node to any other given node along a multinode loop of any desired mode quantity, with each node being capable of and maintained ready to assume the role and function of master node to provide the time-base or master clock for the loop. One node will serve as master node and all other nodes as slave nodes until the master becomes inoperable in its master clock function or until it is removed from the loop, at which time another node will assume the role of master node, and this status will continue as above-indicated. Small loop size is accommodated by adding a suitable delay to retransmitted data at the master node. Each node has clock recovery and both recovered clock/data synchronization means and its on-board master clock/data synchronization means (which latter is close to the same frequency at each node, but independent in frequency and phase at each node) to enable each node to serve as either master or slave node by internal switching selection of communication control output of either recovered clock data or master clock data for use and retransmission at each node, dependent on its instant self-intended role as slave or master.

Master clock data synchronization at the master node is effected by shifting recovered clock data by a selected phase as a function of phase difference between the instant master node master clock and recovered clock at such master node, the selected phase shift being an amount sufficient to enable effective sampling by the master clock, to thereby provide absolute phase synchronization of receive data with master clock for internal serial processing, utilization, and retransmission by the instant master node. Each instant slave node has its own on-board such master clock data synchronizing means which may be maintained on standby, for enabling each assumption of the master node role, as may be required.

Claims

1. A multinode synchronous serial data closed loop communication system, comprising

a plurality of nodes, including at least two synchronous dual function master/slave loop nodes, connected in a closed serial-data sequential synchronous node-to-node communication loop,

each of said dual function master/slave nodes having the dual capability of selectively acting as either a loop master node providing a single loop time base or master clock for synchronous serial data sequential communication between each of said dual function master/slave loop nodes and each of the other of said dual function master/slave nodes, or as a slave node acting to slave in synchronism with said master clock provided by a single selected one of said dual function master/slave nodes which is acting as the instant loop master node,

and means for switching one of said master/slave nodes from slave mode to master mode in response to detection of indication of absence of an effectively operating master node on said loop.

2. A multinode synchronous serial data closed loop communication system according to claim 1, including a plurality of said dual function master/slave nodes.

5. A multinode synchronous serial data closed loop communication system according to claim 1,

each of said dual function master/slave nodes having a selectively loop-time-base-forming master clock, and master clock receive data synchronizing means for synchronizing received data with its respective said selectively loop-time-base-forming master clock.

11. A multinode synchronous serial data closed loop communication system according to claim 1,

3. A multinode synchronous serial data closed loop communication system, comprising,

a plurality of nodes, including at least two synchronous dual function master/slave loop nodes, connected in a closed serial-data sequential synchronous node-to-node communication loop,

each of said dual function master/slave nodes having the dual capability of selectively acting as either a loop master node providing a single loop time base or master clock for synchronous serial data sequential communication between each of said dual function master/slave loop nodes and each of the other of said dual function master/slave nodes, or as a slave node acting to slave in synchronism with said master clock provided by a single elected one of said dual function master/slave nodes which is acting as the instant loop master node,

each of said dual function master/slave nodes having loop master/slave select means responsive to detection of absence of an instant active loop master node on the loop, to effect assumption of loop master node status y each such dual function master slave node.

4. A multinode synchronous serial data closed loop communication system, comprising

a plurality of nodes, including at least one synchronous dual function master/slave loop node, connected in a closed serial-data sequential synchronous node-to-node communication loop,

each of said dual function master/slave nodes having the dual capability of selectively acting as either a loop master node providing a single loop time base or master clock for synchronous serial data sequential communication between each of said dual function master/slave loop nodes and each of the other of said dual function master/slave nodes, or as a slave node acting to slave in synchronism with said master clock provided by a single selected one of said dual function maste/slave nodes which is acting as the instant loop master node,

each of said dual function master/slave nodes having loop master/slave select means responsive to detection of absence of an instant active loop master node on the loop, to effect assumption of loop master node status by each such dual function master/slave node,

each of said dual function master/slave nodes having means for actuating the respective said master/slave select means to master-select mode after passage of a different time period after said detection of absence of an instant active loop master node on the loop, as compared to the corresponding said time period for all others of said dual function master/slave nodes.

6. A multinode synchronous serial data closed loop communication system, comprising,

a plurality of nodes, including at least two synchronous dual function master/slave loop nodes, connected in a closed serial-data sequential synchronous node-to-node communication loop,

each of said dual function master/slave nodes having the dual capability of selectively acting as either a loop master node providing a single loop time base or master clock for synchronous serial data sequential communication between each of said dual function master/slave loop nodes and each of the other of said dual function master/slave nodes, or as a slave node acting to slave in synchronism with said master clock provided by a single electled one of said dual function master/slave nodes which is acting as the instant loop master node,

each of said dual function master/slave nodes having a selectively loop-time-base-forming master clock, and master clock receive data synchronizing means for synchronizing received data with its respective said selectively loop-time-base-forming master clock,

said master clock receive data synchronizing means including

phase-shifted-data-providing means for providing a selectively phase shifted form of data received at its respective said dual function master/slave node, as a function of the phase difference between a form of said received data and said selectively loop-time-base-forming master clock at the respective said dual function master/slave node, by an amount sufficient to enable effective sampling of said selectively phase shifted form of receive data by said selectively loop-time-base-forming master clock at the respective said dual function master/slave node.

7. A multinode synchronous serial data closed loop communication system according to claim 6, said phase-shifted-data-providing means including

means for shifting a form of data received at its respective said node, through a plurality of preselected angles, to form a plurality of selectable differently phase-shifted forms of the data received at the respective said dual function master/slave node,

and means for selecting one of said plurality of selectable differently phase-shifted forms of data as a function of the phase difference between a reference form of the data received at said respective dual function master/slave node and said selectively loop-time-base-forming master clock at the respective said dual function master/slave node.

8. A multinode synchronous serial data closed loop communication system according to claim 7,

in which said reference form of the data received at said respective dual function master/slave node is receive data reclocked by recovered clock to form recovered clock receive data.

9. A multinode synchronous serial data closed loop communication system according to claim 8, further comprising at each of said dual function master/slave nodes,

clock recovery means to form recovered clock in effective slaved frequency and phase synchronism with the instant said loop-time-base-forming master clock at the instant loop master node,

and means for sampling raw received data with said recovered clock to form recovered clock receive data.

10. A multinode synchronous serial data closed loop communication system according to claim 9,

in which said loop master/slave select means at each of said dual function master/slave nodes acts to select either of said master clock receive data and associated said loop-time-base-forming master clock at the respective said dual function master/slave node, or the respective said recovered clock receive data at said associated recovered clock at the respective said dual function master/slave node, for internal processing and/or retransmittal of received data onto said loop, and/or transmittal of new data onto said loop.

12. in which more than one and less than all of said nodes in said loop are dual function master/slave nodes,

and in which said loop includes a fixed slave mode node.

13. A multinode serial data sequential node-to-node synchronous communication system, comprising

a plurality of nodes interconnected in a closed sequential node-to-node synchronous serial data communication loop,

one of said nodes having means for generating a loop-timing-base-forming master clock, and having the capacity and function of acting as the loop master node furnishing a loop time base master clock source for data on said loop, while the other said nodes act as slave nodes slaving to said loop timing base master clock,

said one node having absolute phase synchronizing means which effects absolute phase synchronizing of data received by it from the loop with its own said master clock without necessity, at the respective one node having the capacity and function of acting as the loop master node, for removal and storage of data received from the loop, and retrieval/regeneration from storage and reformatting, of the storage-retrieved/regenerated received data and reinsertion onto the loop of such reformatted storage-retrieved/regenerated received data at said one node, in order to enable retransmission of the received data further along the loop, by said one node when acting as the loop master node.

15. A multinode serial data sequential node-to-node synchronous communication system according to claim 13,

means for shifting a form of data received at said one node by a plurality of preselected angles, to form a plurality of selectable differently phase-shifted forms of the data received at the said one node,

and means for selecting one of said plurality of selectable differently phase-shifted forms of data as a function of the phase difference between a reference form of the data received at said one node and said loop-time-base-forming master clock at said one node.

17. A multinode serial data sequential node-to-node synchronous communication system according to claim 15, including

clock recovery means to form recovered clock in effective slaved frequency and phase synchronism with the data received at said one node and in frequency synchronism with said loop-time-base-forming master clock at said one node,

and means for sampling raw received data with said recovered clock to form recovered clock receive data.

19. A multinode serial data sequential node-to-node synchronous communication system according to claim 17,

in which each of said dual function master/slave nodes has absolute phase synchronizing means for absolute phase synchronizing of data received by it from the loop with its own said master clock.

21. A multinode serial data sequential node-to-node synchronous communication system according to claim 19,

means for shifting a form of data received at the respective said node by a plurality of preselected angles, to form a plurality of selectable differently phase-shifted forms of the data received at the respective said dual function master/slave node,

and means for selecting one of said plurality of selectable differently phase-shifted forms of data as a function of the phase difference between a reference form of the data received at said respective dual function master/slave node and said selectively loop-time-base-forming master clock at the respective said dual function master/slave node.

23. A multinode serial data sequential node-to-node synchronous communication system according to claim 21,

clock recovery means to form recovered clock in effective slaved synchronism with the instant said loop-time-base-forming master clock at the instant said loop master dual function master/slave node,

and means for sampling raw received data with said recovered clock to form recovered clock receive data.

14. A multinode serial data sequential node-to-node synchronous communication system, comprising

a plurality of nodes interconnected in a closed sequential node-to-node synchronous serial data communication loop,

one of said nodes having means for generating loop-time-base-forming master clock, and having the capacity of acting as the loop master node furnishing loop timing base or master clock source for data on said loop, while the other sid nodes act as slave nodes slaving to said loop time base,

said one node having absolute phase synchronizing means for absolute phase synchronizing of data received by it from the loop with its own said master clock,

said absolute phase synchronizing means including phase-shifted-data-providing means for providing a selectively phase-shifted form of data received at the respective said one node, as a function of the phase differences between a form of said received data and said loop-time-base-forming master clock at said one node, by an amount sufficient to enable effective sampling of said selectively phase-shifted form of receive data by said loop-time-base-forming master clock at said one node.

16. A multinode serial data sequential node-to-node synchronous communication system according to claim 14,

in which said reference form of the data received at said one node is receive data reclocked by recovered clock to form recovered clock receive data.

18. A multinode serial data sequential node-to-node synchronous communication system, comprising

a plurality of synchronous dual function master/slaves nodes interconnected in a closed sequential node-to-node synchronous serial data communication loop and each of which master/slave nodes communicates through employment of a master clock from a single one of said master/slave nodes acting as the master clock source for the entire loop,

each of said dual function master/slave nodes having means for generating selectively a loop-time-base-forming master clock, and having the dual capacity of acting as either the loop master node furnishing loop timing base or master clock source for data on said loop, or as a slave node slaving to said loop time base, and having means for self-switching from slave node mode to master node mode as a function of detection of absence of effective operation of a master clock node on the loop.

20. A multinode serial data sequential node-to-node synchronous communication system, comprising

a plurality of synchronous dual function master/slave nodes interconnected in a closed sequential node-to-node synchronous serial data communication loop,

each of said dual function master/slave nodes having means for generating selectively loop-time-base-forming master clock, and having the dual capacity of acting as either the loop master node furnishing loop timing base or master clock source for data on said loop, or as a slave node slaving to said loop time base,

each of said dual function master/slave nodes having absolute phase synchronizing means for absolute phase synchronizing of data received by it from the loop with its own said master clock,

said absolute phase synchronizing means including phase-shifted data providing means for providing a selectively phase-shifted form of data received at its respective said dual function master/slave node, as a function of the phase differences between a form of said received data and the said selectively loop-time-base-forming master clock at the respective said dual function master/slave node, by an amount sufficient to enable effective sampling of said selectively phase-shifted form of receive data by said selectively loop-time-base-forming master clock at the respective said dual function master/slave node.

22. A multinode serial data sequential node-to-node synchronous communication system according to claim 20,

in which said reference form of tthe data received at said respective dua function master/slave node is receive data reclocked by recovered clock to form recovered clock receive data.

24. An absolute phase synchronizer for synchronizing data received at one node of a multinode synchronous loop communication system, with a loop-time-base or master clock at said one node, and which said one node has clock recovery means and means for forming recovered clock receive data, said absolute phase synchronizer comprising

means for comparing the phase of recovered clock relative to said master clock,

coarse phase-shifting means for coarse phase-shifting of the phase of received data as a function of the result of said comparing, by an amount enabling effective successive serial data sampling of received data by said master clock,

and sampling means for successively serially sampling said coarse phase-shifted received data with master clock in absolute phase synchronization with said master clock.

25. An absolute phase synchronizer for synchronizing data received at one node of a multinode synchronous loop communication system, with a loop-time-base or master clock at said one node, and which said one node has clock recovery means and means for forming recovered clock receive data, said absolute phase synchronizer comprising

means for comparing the phase of recovered clock relative to said master clock,

coarse phase shifting means for coarse phase shifting of the phase of received data as a function of the result of said comparing, by an amount enabling effective sampling of received data by said master clock,

sampling means for sampling said coarse phase shifted received data to thereby form master clock-sampled receive data in absolute phase synchronization with said master clock,

said coarse phase-shifting means comprising:

a shift register clocked at a rate which is a selected multiple of the rate of said recovered clock, which shift register has said recovered clock receive data as its input for shifting thereof, and has multiple phase-shifted outputs, each of which outputs represents said recovered clock receive data inputted thereto, shifted by a given phase which is a function of said selected multiple, and of the shift position of each of the respective shift register outputs,

and means for selecting one of said multiple phase-shifted outputs of said shift register as a function of the phase relationship deteced by said phase-comparing means, to thereby enable effective sampling of said selected phase-shifted output by said master clock to thereby enable master clock receive data to be formed, in absolute phase synchronism with said master clock.

27. Absolute phase synchronizing means according to claim 25,

in which said coarse phase-shifting means comprises

a shift register clocked at a rate which is a selected multiple of the rate of said data-synchronized clock, and which shift register has said binary data as its input and has multiple outputs, each of which represents the data inputted thereto shifted by a given phase which is a function of said selected multiple, and of the shift position of the given shift register output,

and means for selecting one of said multiple phase-shifted outputs of said shift register as a function of the phase relationship detected by said phase-comparing means, to enable effective sampling of said selected phase shifted output by said one master clock, to thereby enable master clock binary data to be formed, in absolute phase synchronism with said master clock.

29. A data/clock synchronizer according to claim 27, in which

said coarse phase-shifting means comprises means for shifting the phase of recovered clock-sampled received data to enable center-bit sampling by said master clock,

said sampling means for sampling said coarse phase-shifted received data comprises means for center-bit sampling said phase-shifted recovered clock-sampled received data by said master clock to form master clock-sampled received data in absolute phase relation with said master clock.

31. Apparatus according to claim 29,

said go-ahead detection and generating means comprising a multi-bit binary counter which changes its binary output state to an opposite state from the instant input upon reaching its highest bit count as a function of receipt of a succession of n-bits of one given state, thereby effectively forming a go-ahead token composed of (n-1) bits of said one given state followed by one bit of the opposite state.

32. Apparatus according to claim 29,

multi-bit delay means providing a multi bit delay for said master clock-sampled received data,

said multi-bid delay being at least as great as the bit length of the go-ahead token.

33. Apparatus according to claim 31,

wherein said multi-bit delay is formed by a multi-bit shift register having said coarse phase-shifted received data as an input and which is clocked by the master clock.

34. Apparatus according to claim 32,

said center bit sampling the reclocked received data with the multi-bit shift register first stage to thereby form master clock sampled received data.

36. The method according to claim 34, in which

said forming of said course phase-shifted data is effected by coarse phase-shifting said particular binary data by a plurality of selected coarse angles to provide a plurality of differently coarse phase-shifted binary data selectable outputs,

and selecting for master clock sampling, one of said plurality of selectable outputs as a function of the coarse phase angle difference detected by said comparing of the phase of the master clock with the data-synchronized clock.

26. Absolute phase synchronizing means for phase synchronizing binary data with a master binary clock which said binary data has effectively the frequency of said master clock but which may not be in phase with said master clock comprising:

means for forming a data-synchronized binary clock in synchronism with said binary data,

phase-comparing means for comparing the phase of said data-synchronized binary clock with the phase of said master clock,

coarse phase-shifting means for forming coarse phase-shifted data whose phase is shifted by a phase angle which based on the result of said comparing is an amount enabling effective sampling of said coarse phase-shifted data by said master clock,

and means for sampling said coarse phase-shifted data with master clock to form master clock-sampled received data in absolute phase synchronization with said master clock.

28. For use in a multinode data communication system in which data is serially passed from node to node, and in which a node has serial-to-parallel/parallel-to-serial data conversion means requiring a clock in synchronization with received and transmitted serial data processed by said data conversion means, the improvement of a composite master/slave node data/clock synchronizer capable of operating in either a master or a slave mode, comprising,

clock recovery means for recovering clock from received data and for sampling received data with said recovered clock to thereby form recovered clock-sampled received data in both phase and frequency synchronization with said recovered clock,

master clock means for generating a master clock,

means for comparing the phase of recovered clock relative to said master clock,

coarse phase shifting means for coarse phase-shifting of the phase of received data as a function of the result of said comparing, by an amount enabling effective sampling of received data by said master clock,

sampling means for sampling said coarse phase-shifting received data to thereby form master clock-sampled received data in absolute phase synchronization with said master clock,

and means for selecting one of said master clock or said recovered clock as an output for application as an input to said data conversion means and for concomitantly selecting the associated said master clock-sampled received data or said recovered clock-sampled received data as an output for application as an input to said data conversion means.

30. For use in a multinode data communication system in which data is serially passed from node to node, and in which a node has serial-to-parallel/parallel-to-serial data conversion means requiring a clock in synchronization with received and transmitted serial data processed by said data conversion means, the improvement of a composite master/slave node data/clock synchronizer capable of operating in either a master or a slave mode, comprising

clock recovery means for recovering clock from received data and for sampling received data with said recovered clock to thereby form recovered clock-sampled received data in both phase and frequency synchronization with said recovered clock,

master clock means for generating a master clock,

means for comparing the phase of recovered clock relative to said master clock,

coarse phase-shifting means for coarse phase-shifting of the phase of received data as a function of the result of said comparing, by an amount enabling effecting sampling of received data by said master clock,

sampling means for sampling said coarse phase-shifted received data to thereby form master clock-sampled received data in absolute phase synchronization with said master clock,

means for selecting one of said master clock or said recovered clock as an output for application as an input to said data conversion means and for concomitantly selecting the associated said master clock-sampled received data or said recovered clock-sampled received data as an output for application as an input to said data conversion means,

and go-ahead detection and generating means for detecting absence of both a multi-bit go-ahead token and intelligence-bearing data, and for generating and inserting a go-ahead token into the data stream upon detection of absence of said go-ahead token and intelligence-bearing data.

35. The method of absolutely synchronizing the phase of binary data with a binary master clock in which the binary data has effectively the frequency of the master clock but may be out of phase with the master clock, comprising

forming a binary data-synchronized clock synchronized with said particular binary data,

comparing the phase of said data-synchronized clock with the phase of said master clock,

forming coarse phase-shifted binary data which is coarse phase-shifted relative to said particular binary data if and as may be required as a function as the coarse phase angle difference detected by said comparing and by a coarse amount enabling effective sampling thereof by said master clock,

and sampling said course phase-shifted data to thereby provide said binary data in absolute phase synchronization with said master binary clock.

37. The method of absolute phase synchronizing receive data from one location with a master clock at a second location in which receive clock is the receive clock at said second location and is in substantial frequency synchronism with said master clock but of no definite phase relationship relative to master clock, comprising

generating a master clock in association with said second location, and which master clock is the time-base source of clock for said receive data,

and absolute phase-synchronizing said receive data to absolute phase synchronism with said master clock by effectively sampling said receive data with master clock after coarse phase-shifting said receive data by an amount sufficient to enable effective sampling thereof by said master clock.

38. The method of absolute phase synchronizing receive data from one location with a master clock at a second location in which receive clock is the receive clock at said second location and is in substantial frequency synchronism with said master clock but of no definite phase relationship relative to master clock, comprising

generating a master clock associated with said second location and which master clock is the time-base source of clock for said receive data,

comparing the phase of said receive clock with the phase of said master clock,

absolute phase-synchronizing said receive data to absolute phase synchronism with said master clock,

said absolute phase-synchronizing being effected by coarse phase-shifting of said receive clock synchronized receive data relative to said master clock by an amount which, based on the phase difference between said receive clock and said master clock as indicated by said comparing of phases, is sufficient to enable effective sampling of said data by said master clock,

and effectively sampling the resultant said phase-shifted data with said master clock to thereby synchronize said receive data in absolute phase with said master clock.

40. The method according to claim 38, further comprising

carrying out the steps of claim 38, at each of a plurality of node locations serially interconnected along a loop from which said receive data is received,

at one of said node locations acting as instant master mode, selecting said master clock receive data and transmitting such master clock receive data back onto the loop,

and at all other instant loop node locations feeding the recovered receive clock-synchronized receive data back onto the loop.

39. The method of synchronizing receive data with master clock, comprising

generating a master clock of substantially constant frequency,

generating a selectively variable frequency slave clock having a nominal frequency substantially corresponding to said master clock,

comparing the phase relationship of said variable frequency slave clock with data transitions of receive data,

selectively successively varying the frequency and phase of said variable frequency slave clock as a function of the phase relationship of said variable frequency slave clock with said data transitions of said receive data, to form recovered receive clock in substantial frequency synchronism with said receive data,

reclocking said receive data with said variable frequency slave clock by sampling said receive data with said recovered receive clock formed by the updated said variable frequency clock to form recovered clock-synchronized receive data,

comparing the phase of said recovered receive clock with the phase of said master clock,

selectively shifting the phase of said recovered receive clock-synchronized receive data as a function of the amount of phase difference between said master clock and said recovered receive clock by an amount sufficient to enable effective sampling of said recovered receive clock-synchronized receive data by said master clock,

and effectively sampling the resultant phase-shifted said recovered receive clock-synchronized receive data, to thereby form receive data in absolute phase synchronism with said master clock.