Code reader

• US 4,680,457 A
• Filed: 03/07/1985
• Issued: 07/14/1987
• Est. Priority Date: 03/07/1985
• Status: Expired due to Term

• Current Assignee: InfoSight Corporation
• Original Assignee: Telesis Controls Corporation
• Inventors: Robertson, John A.
• Primary Examiner(s): Pitts, Harold I.
• Application Number:
  US06/708,974
• Time in Patent Office: 859 Days
• Field of Search: 235/463, 235/470, 235/471, 235/472
• US Class Current: 235/470
• CPC Class Codes: G06K 7/0166 by means of clock-signals derived from the code marks, e.g. self-clocking code
• CPC Class Codes: G06K 7/10851 Circuits for pulse shaping, amplifying, eliminating noise signals, checking the function of the sensing device basic electronic circuitry H03
• CPC Class Codes: G06K 7/14 using light without selection of wavelength, e.g. sensing reflected white light G06K7/10831 - G06K7/1097 take precedence

Abstract

A code reader and method which is capable of reading "black-on-black" codes such as bar codes which are molded in the surface of an object. The code is illuminated so as to provide light-to-shadow transitions which are read by an imaging device such as a video camera. The resultant video signal transitions representing light-to-dark transitions are differentiated and converted to a train of pulses which are submitted to a delay line sequencing network to develop a series of timing signals. These timing signals are utilized to operate a sampling network to derive 0-bit and 1-bit code information which is submitted serially to a serial-to-parallel shift register to permit code reading by a microcomputer function. Legality checks are carried out with respect to sampling and the developed work and quiescent zones are developed with respect to the start and stop of a given code sequence.

Claims

1. Apparatus for reading a code provided as a word deriving sequence of radiation definable transitions carried on an object and selectively spaced from said first to last in accordance with a predetermined ratio defining first-bit and second-bit information, comprising:

imaging means for imaging at least a portion of said code carrying object for generating an imaged output signal having image signal transitions occurring in a time spaced sequence corresponding with said code sequence of spaced transitions;

signal treatment means responsive to said imaging means for converting said image signal transition into a corresponding train of pulses;

sequencer means for receiving said train of pulses and having a sequence of timing stages positioned from first to last for selectively delaying the transmission of said pulses therethrough to establish a sequence of pulse occurrence timing signals commencing with said train of pulses;

first sampling network means responsive to a given said timing signal established in conjunction with a sampling said timing stage positioned subsequent in said sequence from said first stage for deriving a valid first-bit condition following a first interval corresponding with a said time spaced sequence representing said first-bit select spacing and responsive to a next said timing signal occurring during said valid first-bit condition established at a next pulse said timing stage position prior in said sequence to said sampling timing stage to provide a first-bit datum;

second sampling network means responsive simultaneously with said first sampling network means to said given timing signal for deriving a valid second-bit condition following a second interval corresponding with a said time spaced sequence representing said second-bit select spacing and responsive to said next timing signal occurring during said valid second-bit condition established by said next pulse timing stage to provide a second bit datum;

serial-to-parallel alignment means responsive to each said first-bit datum and said second-bit datum in the sequence of their occurrence for deriving a serial alignment corresponding therewith defining a word and having a parallel output corresponding therewith representing said word; and

control means responsive to said parallel output for carrying out the decoding thereof.

2. The apparatus of claim 1 in which said sequencer means includes sequence monitoring stage means responsive to the initial one of said pulse occurrence timing signals of said last timing stage commencing a word defining sequence thereof to derive a datum representing the initial one in said sequence of occurrence.

3. The apparatus of claim 2 in which:

said control means includes restart means responsive to a restart signal for clearing said serial-to-parallel alignment means; and

including error detect means responsive to the occurrence of a said next timing signal in the simultaneous absence of said valid first-bit condition and said valid second-bit condition for effecting the derivation of said restart signal.

4. The apparatus of claim 1 in which said signal treatment means includes means for differentiating said imaged signal transitions to derive differentiated transitions and means for converting said differentiated transitions to said train of pulses.

5. The apparatus of claim 1 in which:

said first sampling network comprises;

first monostable multivibrator means for receiving said given timing signal subsequent to being cleared and responsive to have a first output following said first interval,

first tolerance monostable multivibrator means responsive to said first output, subsequent to being cleared, for deriving said valid first-bit condition for a predetermined first tolerance interval, and

first latch means responsive, subsequent to being cleared, to said next timing signal in the presence of said valid first-bit condition for providing said first-bit datum; and

said second sampling network comprises;

second monostable multivibrator means for receiving said given timing signal subsequent to being cleared and responsive to have a second output following said second interval,

second tolerance monostable multivibrator means responsive to said second output subsequent to being cleared for deriving said valid second-bit condition for a predetermined second tolerance interval, and

second latch means responsive, subsequent to being cleared, to said next timing signal in the presence of said valid second-bit condition for providing said second-bit datum.

6. The apparatus of claim 5 in which:

said sampling timing stage is the last of said sequence thereof;

said first and second latch means are cleared upon the occurrence of said given timing signal;

said first and second tolerance monostable multivibrator means are cleared upon the occurrence of a timing signal provided by a said timing stage positioned in said sequence subsequent to said first stage;

said first and second monostable multivibrator means are cleared upon the occurrence of a timing signal of a said timing stage positioned in said sequence subsequent to said first stage and prior to said timing stage providing said timing signal clearing said first and second tolerance monostable multivibrators; and

said next timing signal is provided upon the occurrence of a pulse input to said first timing stage.

7. The apparatus of claim 5 in which:

said control means includes restart means responsive to a restart signal for clearing said serial-to-parallel alignment means;

legal output means coupled with said first and second latch means and responsive to the presence of a datum output thereof to derive a legal bit status condition and having an illegal bit status condition in the absence of a said datum output;

error status means responsive, subsequent to being cleared, to said illegal bit status condition and to the occurrence of a timing signal provided by a said timing stage positioned in said sequence subsequent to said first stage and prior to said last stage for deriving said restart signal.

8. The apparatus of claim 7 in which:

said sampling timing stage is the last of said sequence thereof;

said first and second latch means and said error status means are cleared upon the occurrence of said given timing signal;

said first and second tolerance monostable multivibrator means are cleared upon the occurrence of a timing signal provided by a said timing stage positioned in said sequence subsequent to said first stage;

said first and second monostable multivibrator means are cleared upon the occurrence off a timing signal of a said timing stage positioned in said sequence subsequent to said first stage and prior to said timing stage providing said timing signal clearing said first and second tolerance monostable multivibrators; and

said next timing signal is provided upon the occurrence of a pulse input to said first timing stage.

9. The apparatus of claim 1 in which:

said sequencer means includes retriggerable sequence monitoring means responsive to each said timing signal derived from said last timing stage for commencing the timing of a predetermined interval selected as greater than the pulse interval of said pulse occurrence sequence and having a quiet at the end condition upon the occurrence of said time-out;

said control means includes;

computer means coupled with said serial-to-parallel alignment means parallel output for reading said output in response to a data ready signal and for providing a search signal;

bracket test gate means for evaluating said bit datum at select positions of said parallel output with respect to predetermined check values thereof to derive a bracked test output in the presence of correspondence therebetween and bracket error condition in the absence of such correspondence;

search mode status means responsive to said search signal to derive a search mode condition;

running mode status means responsive to said bracket test output, said search condition and the occurrence of a said timing signal to derive a running mode condition and responsive to said running mode condition, said quiet at the end condition for effecting derivation of said data ready signal.

10. The apparatus of claim 9 in which:

said sequencer means includes start timer means responsive to said quiet at the end condition for commencing the timing of a predetermined interval and deriving a quiet at the start condition at the conclusion of said time-out;

said control means includes restart means responsive to a restart signal for clearing said serial-to-parallel alignment means, and means responsive to said quiet at the start condition in the presence of said running mode condition to derive said restart signal.

11. The apparatus of claim 10 in which said control means includes means for deriving said restart signal in response to said bracket error condition.

12. The apparatus of claim 9 including means for enabling said sequencer means in response to said search mode condition.

13. A system for reading a code at the surface of an object provided as a word deriving sequence of three-dimensional code components selectively spaced from first to last in a spacing ratio defining first-bit and second-bit information, comprising:

radiation source means for exposing said surface to radiation from a location deriving radiation definable transitions at said code components;

imaging means for imaging said surface to generate a video type output signal having transitions occurring in a time spaced sequence corresponding with said code component spacing;

signal treatment means responsive to said imaging means for differentiating the said transition thereof and converting said differentiated transition to a corresponding train of pulses;

sequencer means for receiving said train of pulses and having a sequence of timing stages from first to last for selectively delaying the transmission of said pulses therethrough to establish a sequence of pulse occurrence timing signals;

a sampling circuit including;

first sampling network means having a first tansition interval timing stage responsive to a given said timing signal established with respect to a sampling said timing stage positioned subsequent in said sequence from said first stage, or providing a first output following an interval corresponding with a said time spaced sequence representing said first-bit select spacing,

a first tolerance interval timing stage responsive to said first output for deriving a valid first-bit condition for a predetermined first tolerance interval,

first latch means responsive to a next said timing signal occurring during said valid first-bit condition corresponding with a next pulse said timing stage position located prior in said sequence to said sampling timing stage to provide a first-bit datum, and

second sampling network means having a second transition interval timing stage responsive to said given timing signal for providing a second output following an interval corresponding with a said time spaced sequence representing said second-bit select spacing,

a second tolerance interval timing stage responsive to said second output for deriving a valid second-bit condition for a predetermined second tolerance interval, and

second latch means responsive to said next timing signal occurring during said valid bit condition to provide a second bit datum;

serial-to-parallel alignment means responsive to each said first-bit datum and said second-bit datum in the sequence of their occurrence for deriving a parallel output representing a said word; and

control means responsive to treat said parallel output.

14. The system of claim 13 in which:

said radiation source is a strobe light actuable to provide illumination along a given axis of light propagation; and

said imaging means is a video signal generating device having entrance optics the control axis of which is aligned substantially normal to said given axis.

15. The system of claim 14 in which said strobe light is actuated substantially in synchronism with the field rate of said video signal.

16. The system of claim 13 in which said sequencer means includes sequence monitoring stage means responsive to the initial one of said pulse occurrence timing signals of said last timing stage commencing a word defining sequence thereof to derive a datum representing the initial one in said sequence of occurrence.

17. The system of claim 13 in which:

said control means includes restart means responsive to a restart signal for clearing said serial-to-parallel alignment means; and

said sampling circuit includes error detect means responsive to the occurrence of a said next timing signal in the simultaneous absence of said valid first-bit condition and said valid second-bit condition for effecting the derivation of said restart signal.

18. The system of claim 13 in which:

said control means includes restart means responsive to a restart signal for clearing said serial-to-parallel alignment means;

said sampling circuit includes legal output means coupled with said first and second latch means and responsive to the presence of a datum output thereof to derive a legal bit status condition and having an illegal bit status condition in the absence of a said datum output;

error status means responsive, subsequent to being cleared, to said illegal bit status condition and to the occurrence of a timing signal provided by a said timing stage positioned in aid sequence subsequent to said first stage and prior to said last stage for deriving said restart signal.

19. The apparatus of claim 13 in which:

said sequencer means includes retriggerable sequence monitoring means responsive to each said timing signal derived from said last timing stage for commencing the timing of a predetermined interval selected as greater than the pulse interval of said pulse occurrence sequence and having a quiet at the end condition upon the occurrence of said time-out;

said control means includes;

computer means coupled with said serial-to-parallel alignment means parallel output for reading said output in response to a data ready signal and for providing a search signal;

bracket test gate means for evaluating said bit datum at select positions of said parallel output with respect to predetermined check values thereof to derive a bracked test output in the presence of correspondence therebetween and bracket error condition in the absence of such correspondence;

search mode status means responsive to said search signal to derive a search mode condition;

running mode status means responsive to said bracket test output, said search condition and the occurrence of a said timing signal to derive a running mode condition and responsive in said running mode condition, said quiet at the end condition for effecting derivation of said data ready signal.

20. The apparatus of claim 19 in which:

said sequencer means includes start timer means responsive to said quiet at the end condition for commencing the timing of a predetermined interval and deriving a quiet at the start condition at the conclusion of said time-out;

said control means includes restart means responsive to a restart signal for clearing said serial-to-parallel alignment means, and means responsive to said quiet at the start condition in the presence of said running mode condition to erive said restart signal.

21. The method for reading a code at the surface of an object provided as a word deriving sequence of radiation definable transitions selectively spaced in accordance with a predetermined ratio defining first-bit and second-bit information comprising the steps of:

imaging said surface with a video device to generate an output signal having transitions occurring in a time spaced sequence corresponding with said code sequence of spaced transitions;

forming a train of pulses from said output signal transitions;

applying said train of pulses to a sequence of timing stages from first to a sampling stage to establish a sequence of pulse occurrence timing signals;

applying a given timing signal associated with said sampling stage to a first sampling network having a valid first-bit condition during a first tolerance interval following a first interval corresponding with a said time spaced sequence representing said first-bit select spacing;

simultaneously applying said given timing signal to a second sampling network having a valid second-bit condition during a second tolerance interval following a second interval corresponding with a said time spaced sequence representing said second bit spacing;

deriving a first-bit datum when the next pulse of said train of pulses following said given timing signal occurs during said first tolerance interval;

deriving a second-bit datum when the said next pulse occurs during said second tolerance interval;

arranging each said derived first-bit datum and said second-bit datum serially in the sequence of their occurence to develop a said word; and

reading said word.

22. The method of claim 21 including the steps of:

differentiating said output signal transitions to provide differentiated transition signals; and

forming said train of pulses from said differentiated transition signals.

23. The method of claim 21 including the step of indicating the presence of a said first-bit datum upon the occurrence of the first said given timing signal developed from a word defining sequence of said train of pulses.

24. The method of claim 21 including the steps of

generating an error signal when said first-bit datum or said second-bit datum are not derived upon the occurrence of said next pulse;

and

cancelling said arrangement of said first-bit datum and said second-bit datum in response to said error signal.

25. The method of claim 21 including the step of providing a quiescent interval of predetermined length upon the completion of propagation of a word defining sequence of said train of pulses through said timing stages.

26. The method of claim 21 including the step of illuminating said surface with a source of light having an axis of light propagation arranged at an angle with respect to said surface to derive said transitions as light-to-shadow transitions.