Inverter for use with solar arrays

• US 4,680,690 A
• Filed: 05/23/1986
• Issued: 07/14/1987
• Est. Priority Date: 10/19/1984
• Status: Expired due to Fees

• Current Assignee: Arthur F. Dickerson
• Original Assignee: Arthur F. Dickerson
• Inventors: Dickerson, Arthur F.
• Primary Examiner(s): Salce, Patrick R.
• Assistant Examiner(s): Jones, Judson H.
• Application Number:
  US06/866,863
• Time in Patent Office: 417 Days
• Field of Search: 363/40, 363/43, 363/97, 363/98, 363/131, 363/132, 323/906, 307/260
• US Class Current: 363/43
• CPC Class Codes: H02M 7/49 Combination of the output voltage waveforms of a plurality of converters
• CPC Class Codes: Y02E 10/56 Power conversion systems, e.g. maximum power point trackers
• CPC Class Codes: Y10S 323/906 Solar cell systems

Abstract

A controlled switching system for converting the output of several photovoltaic solar arrays into a polyphase alternating electric current. Each array is utilized 100% of the time, and at any particular instant only one array or no array is feeding a particular phase. The specific line to which an array is connected is altered in a cyclic manner by the switching system to synthesize the polyphase current. Energy is not stored in the switching system, but instead is made available as polyphase electric current as soon as it is generated by the photovoltaic arrays. Each phase approximates a sine wave to an extent that is limited by the number of arrays. For the closest approximation, the arrays must be configured to have prescribed voltages and currents. Alternatively, a single array may be partitioned electrically in such a way that the desired voltages and currents are attained.

Claims

1. A system for generating a six phase alternating current on the lines L₁, L₂ . . . L₆, comprising in combination:

a first high power array having a positive terminal and having a negative terminal denoted by D₁ ;

a first low power array having a positive terminal and having a negative terminal denoted by D₂, the positive terminals of said first high power array and of said first low power array being connected to a common positive terminal denoted by C⁺ ;

a second high power array having a negative terminal and having a positive terminal denoted by D₁ '"'"';

a second low power array having a negative terminal and having a positive terminal denoted by D₂ '"'"', the negative terminals of said second high power array and of said second low power array being connected to a common negative terminal denoted by C^- ;

switching means connected to the terminals D₁, D₂, C⁺, D₁ '"'"', D₂ '"'"', and C^- and connected to the lines L₁, . . . L₆ for generating a first phase A on the line L₁ by

(a) connecting D₂ '"'"' to L₁ for an interval of 30°

starting at 0° and

again at 150°

(b) connecting D₁ '"'"' to L₁ for an interval of 30°

starting at 30° and

again at 120°

(c) connecting C⁺ to L₁ for an interval of 60°

starting at 60°

(d) connecting D₂ to L₁ for an interval of 30°

starting at 180° and

again at 330°

(e) connecting D₁ to L₁ for an interval of 30°

starting at 210° and

again at 300°

(f) connecting C^- to L₁ for an interval of 60°

starting at 240°

,

for generating a second phase B on the line L₂ by repeating steps (a) through (f) with L₂ substituted for L₁ and with 120°

added to all of the starting phases, for generating a third phase C on the line L₃ by repeating steps (a) through (f) with L₃ substituted for L₁ and with 240°

added to all of the starting phases, for generating a fourth phase A on the line L₄ by repeating steps (a) through (f) with L₄ substituted for L₁ and with 180°

added to all of the starting phases, for generating a fifth phase B on the line L₅ by repeating steps (a) through (f) with L₅ substituted for L₁ and with 300°

added to all of the starting phases, and for generating a sixth phase C on the line L₆ by repeating steps (a) through (f) with L₆ substituted for L₁ and with 420°

added to all of the starting phases.

2. The system of claim 1 wherein said first and second high power arrays together supply approximately 82% of the dc power applied to said switching means, and wherein said first and second low power arrays together supply approximately 18% of the dc power applied to said switching means.