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Virtual memory address translation mechanism with combined hash address table and inverted page table

  • US 4,680,700 A
  • Filed: 12/19/1986
  • Issued: 07/14/1987
  • Est. Priority Date: 12/07/1983
  • Status: Expired due to Term
First Claim
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1. A data processing system comprising:

  • a central processing unit for accessing information stored in page frames by providing a virtual memory address from a virtual memory address space, said virtual memory address space including a plurality of page frame addresses,a first memory for storing information organized as a plurality of page frames and accessible by memory addresses represented by a real memory address space and wherein the virtual memory address space includes a substantially larger number of page frames than the real memory address space;

    means connected to the central processing unit and the first memory for converting virtual memory addresses received from the central processing unit into real memory addresses for accessing information from single page frames from said first memory, said converting means including;

    means for hashing a selected virtual address to produce a hashed address;

    a first table having a list of hashed addresses each with a corresponding predetermined initial virtual address and a pointer to an entry in a second table;

    said second table having a list of virtual addresses corresponding to the initial virtual addresses in the first table and further having a location in the second table corresponding directly to a unique page frame in the real memory address space and each virtual address including a corresponding link address, said link address connecting a plurality of noncontiguous virtual addresses that when hashed produce the same hashed address; and

    means for receiving an input virtual memory address, hashing said input virtual memory address with said hashing means to produce an input hashed address, selecting a location in said first table in accordance with said input hashed address, searching the corresponding linked addressed locations until the input virtual memory address is located, locating the corresponding input virtual address in the second table and its corresponding real address.

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