Interface circuit for connecting peripheral equipment to a computer terminal

• US 4,680,732 A
• Filed: 07/23/1982
• Issued: 07/14/1987
• Est. Priority Date: 07/23/1982
• Status: Expired due to Term

• Current Assignee: AMD Corp (Advanced Micro Devices, Inc.)
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: DiCenzo, Daniel A.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/401,441
• Time in Patent Office: 1,817 Days
• Field of Search: 377/73, 377/81, 377/44, 377/52, 377/108, 364/200 MS File, 364/900 MS File
• US Class Current: 710/62
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 3/002 Specific input/output arrangements not covered by G06F3/01 - G06F3/16 other optical apparatus G02B27/00

Abstract

An electronic interface controller for coupling peripheral equipment, such as a keyboard, printer, or magnetic stripe reader, through a financial terminal to a financial computer system. The interface controller selects the peripheral equipment to be utilized, prescribes the operating mode, and establishes the timing and synchronization of the data transfer. Among its features the invention also includes a unique implementation of D-type flip-flops, with logic feedback, to create synchronous binary counters of selectable modulos.

Claims

1. An interface controller, connected between peripheral equipment and a computer terminal, for selectively coupling plural pieces of peripheral equipment to the computer terminal, comprising:

a bidirectional bus connecting the interface controller to the terminal;

means for synchronizing the timing of the interface controller with the terminal, connected to the terminal and to elements within the interface controller;

means responsive to control signals from the terminal for selecting the peripheral equipment to be operated and the operational direction of said bidirectional bus;

firmware means directly addressable by the terminal for modifying the control signals, which are generated in the terminal and are used to control the means for selecting, to correspond with the peripheral equipment; and

means for receiving asynchronous serial data from selected asynchronous data generating type peripheral equipment and synchronously coupling the data in a parallel format to the terminal over said bidirectional bus.

2. The apparatus recited in claim 1, further comprising:

peripheral equipment means for receiving a coded data bit pattern from the terminal connected to said bidirectional bus, transmitting the pattern through peripheral equipment capable of altering the bit pattern, and returning an altered bit pattern to the terminal.

3. The apparatus as recited in claim 2, further comprising:

means for receiving synchronized parallel data on said bidirectional bus and synchronously coupling the data in an expanded serial format to a peripheral equipment printer.

4. The apparatus recited in claim 3, wherein:

said firmware means addressable by the terminal for modifying the control signals is an expanded instruction set in a programmed memory addressable by the terminal over said bidirectional bus.

5. The apparatus recited in claim 4, wherein:

said means for receiving asynchronous serial data from selected asynchronous data generating type peripheral equipment includes a serial shift register, a source of clocking signals generated in said data generating type peripheral equipment in time correspondence with the serial data generated therein, a parallel shift register coupled to said serial shift register, and a frequency divider for receiving said clocking signals generated in said data generating type peripheral equipment and generating output signals to cause the transfer of data between said serial shift register and said parallel shift register.

6. The apparatus recited in claim 5, wherein:

said means for receiving synchronous parallel data on said bidirectional bus includes a parallel shift register, a source of clocking signals generated in the terminal, frequency dividers coupled to said source of clocking signals, logic circuit means coupled to said source of clocking signals and said frequency dividers for arranging the timing of the frequency dividers to blank the leading and trailing ends of the data after converting data from parallel to serial format, and means for generating a validatiion signal coinciding in time with the data in its serial format.

7. The apparatus recited in claim 6, wherein:

said frequency dividers are modulo X counting devices, wherein 2^n-1 <

X≦

2ⁿ, having n D-type flip-flops, a source of common clocking signals, and feedback logic means for connecting the output terminals of the D-type flip-flops with their D input terminals to generate binary signals at the output terminals having X nonrepetitive binary patterns.