Process for manufacture of high power MOSFET with laterally distributed high carrier density beneath the gate oxide

• US 4,680,853 A
• Filed: 05/30/1986
• Issued: 07/21/1987
• Est. Priority Date: 08/18/1980
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Lidow, Alexander, Herman, Thomas
• Primary Examiner(s): Ozaki, George T.
• Application Number:
  US06/869,109
• Time in Patent Office: 417 Days
• Field of Search: 29/571, 29/576 B, 29/591, 148/187
• US Class Current: 438/268
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A high power MOSFET structure consists of a plurality of source cells distributed over the upper surface of a semiconductor chip, with a drain electrode on the bottom of the chip. Each of the source cells is hexagonal in configuration and is surrounded by a narrow, hexagonal conduction region disposed beneath a gate oxide. The semiconductor material beneath the gate oxide has a relatively high conductivity, with the carriers being laterally equally distributed in density beneath the gate oxide. The high conductivity hexagonal channel is formed in a low conductivity epitaxially formed region and consists of carriers deposited on the epitaxial region prior to the formation of the source region. Symmetrically arranged gate fingers extend over the upper surface of the device and extend through and along slits in the upper source metallizing and are connected to a polysilicon gate grid which overlies the gate oxide.

Claims

1. A process for fabricating a power semiconductor device, comprising the steps of:

(a) providing a wafer having first and second layers, said first layer being of one conductivity type and having a greater resistivity than said second layer;

(b) forming a plurality of spaced deep base regions by introducing into said first layer, through respective dopant windows, dopant of the opposite conductivity type, and thermally driving said dopant to substantially its full final depth in said first layer;

(c) thereafter forming a common region between adjacent deep base regions by introducing a layer of dopant of said one conductivity type into said first layer and thermally driving said dopant to a depth less than said final depth of said opposite conductivity type dopant, whereby the doping concentration in said common region has a constant value laterally across the region of said first layer which contains said common region;

(d) forming respective shallow base regions laterally aaround the respective lateral peripheries of said plurality of deep base regions and forming a respective source region within each of said respective shallow base regions;

(e) providing a dielectric layer atop said common region and on adjacent portions of said shallow base and source regions;

(f) providing a gate electrode atop said dielectric layer; and

(g) contacting said source regions with electrically conductive materal to form a source electrode.

2. The process of claim 1, wherein said introduction of dopant to form said deep base regions comprises implantation of dopant of said opposite conductivity type into said first layer.

3. The process of claim 2, wherein said introduction of dopant to form said deep base regions comprises implantation of dopant in a dosage range of 5×

10¹³ to 1×

10¹⁵ dopant atoms per square centimeter.

4. The process of claim 1, wherein said introduction of dopant to form said common region comprises implanation of dopant of said one conductivity type into said first layer.

5. The process of claim 4, wherein said introduction of dopant to form said common region comprises implantation of dopant in a dosage range from 1×

10¹¹ to 1×

10¹⁴ dopant atoms per square centimeter.

6. The process of claim 1, wherein said one conductivity type comprises N-conductivity type, and said opposite conductivity type comprises P-conductivity type.

7. A process for fabricating a power MOSFET, comprising the steps of:

(a) providing a wafer of one conductivity type having first and second layers, said first layer being of low conductivity relative to said second layer;

(b) forming a plurality of spaced deep base regions by introducing into said first layer, through respective dopant windows, dopant of the opposite conductivity type, and thermally driving said dopant to substantially its full final depth in said first layer;

(c) thereafter forming a common region between adjacent deep base regions by introducing a layer of dopant of said one conductivity type into said first layer and thermally driving said dopant to a depth less than said final depth of said opposite conductivity type dopant, whereby the doping concentration in said common region has a constant value laterally across the region of said first layer which contains said common region;

(d) forming respective shallow base regions laterally around the respective lateral peripheries of said plurality of deep base regions and forming a respective source region within each of said respective shallow base regions;

(e) providing a dielectric layer atop said common region and on adjacent portions of said shallow base and source regions;

(f) providing a gate electrode atop said dielectric layer;

(g) contacting said source regions with electrically conductive material to form a source electrode; and

(h) contacting said second layer with electrically conductive material to form a drain electrode.

8. The process of claim 7, wherein said introduction of dopant to form said deep base regions comprises implantation of dopant of said opposite conductivity type into said first layer.

9. The process of claim 8, wherein said introduction of dopant to form said deep base regions comprises implantation of dopant in a dosage range of 5×

10¹³ to 1×

10¹⁵ dopant atoms per square centimeter.

10. The process of claim 7, wherein said introduction of dopant to form said common region comprises implantation of dopant of said one conductivity type into said first layer.

11. The process of claim 10, wherein said introduction of dopant to form said common region comprises implantation of dopant in a dosage range from 1×

10¹¹ to 1×

10¹⁴ dopant atoms per square centimeter.

12. The process of claim 7, wherein said one conductivity type comprises N-conductivity type, and said opposite conductivity type comprises P-conductivity type.