Insulated gate device with configured emitter contact pad

• US 4,682,195 A
• Filed: 09/30/1985
• Issued: 07/21/1987
• Est. Priority Date: 09/30/1985
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: General Electric Company
• Inventors: Yilmaz, Hamza
• Primary Examiner(s): Clawson, Jr., Joseph E.
• Application Number:
  US06/781,383
• Time in Patent Office: 659 Days
• Field of Search: 357/23.4, 357/23.14, 357/41, 357/52, 357/68
• US Class Current: 257/144
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

The construction of a semiconductor insulated gate device (IGT) is altered to avoid cell latching problems assisted with "hot spot" sites where an atypically high density reverse current tends to flow. IGT cells adjacent these sites are totally or partially disabled by eliminating emitter regions therein to thereby remove any emitter-base junctions from the paths along which the high density reverse current flows. Also the area of emitter electrode ohmic contact is increased at these "hot spot" sites to effectively divert reverse from neighboring, forward current conducting, active cells and thus reduce the density of reverse flow therethrough to safe levels.

Claims

1. In a semiconductor device comprising a silicon semiconductor substrate having a major surface overlying a drift region of first conductivity type;

a plurality of active cells for conducting a main device forward current, each of said cells including a base region of second conductivity type extending from said major surface into said drift region and an emitter region of said first conductivity type extending from said major surface into said base region forming an emitter-base PN junction therewith;

a distributed gate electrode insulatingly spaced from said major surface and overlying a selected portion of each of said cells such that a voltage applied to said gate electrode creates an electric field that controls the magnitude of said main device current;

an emitter electrode electrically insulated from said gate electrode and making ohmic contact with exposed portions of said base and emitter regions of each of said cells at said major surface, said emitter electrode including a metallic emitter pad spaced from said major surface by an insulating layer;

a blocking region of second conductivity type extending from said major surface into said drift region and underlying said emitter pad;

said emitter pad including a first portion disposed in ohmic contact with said blocking region;

the improvement comprising;

said first portion of the emitter pad being disposed so as to surround a second portion of the emitter pad, said second portion of the emitter pad including a plurality of contact portions extending through said insulating layer to make ohmic contact with said blocking region, said contact portions being substantially uniformly distributed over the area of said second portion.