Synchronous data transmission method and device implementing same
First Claim
1. A synchronous data transmission method employing an MB 1C 1F type code for coding each M bits of binary data to be transmitted into an M+2 bit code word, said method steps of:
- dividing the binary data to be transmitted into successive blocks of M bits each (where M is an even integer);
adding to each block a frame bit and a complement bit to form an intermediate word, said frame bit having a value determined in accordance with a parity of each block of M bits;
determining a word digital sum (WDS) in accordance with the difference between the number of marks (logic
1) and spaces (logic
0) of said intermediate word and complement bit;
determining a running digital sum (RDS) in accordance with the difference between the number of ones and zeros in the data already encoded;
complementing said intermediate word in accordance with a comparison of the signs of WDS and RDS, while changing the value of said complement bit, if necessary, to indicate whether said intermediate word has been complemented or not; and
combining said complement bit and said complemented intermediate word to form an output code word to be transmitted having M+2 bits.
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Accused Products
Abstract
A synchronous data transmission method uses an MB 1C 1F type binary-binary code in which the binary data to be transmitted is subdivided into successive blocks of M bits complemented when they feature a disparity (marks minus spaces) of the same sign as the data already encoded, to which is added a complement bit indicating if complementing has been applied and a frame bit consisting of a parity bit enabling the subdivision into blocks carried out at the encoding stage to be recovered at the decoding stage. The encoder has at the input a demultiplexer carrying out the subdivision into blocks followed by circuits for computing the word digital sum and parity and the running digital sum, together with an inverter circuit which processes the blocks from the multiplexer and their parity bit under the control of a complementing decision circuit and a multiplexer transforming the encoded binary signal from the inverter circuit into an isochronous sequence to which a frame bit is added.
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Citations
12 Claims
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1. A synchronous data transmission method employing an MB 1C 1F type code for coding each M bits of binary data to be transmitted into an M+2 bit code word, said method steps of:
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dividing the binary data to be transmitted into successive blocks of M bits each (where M is an even integer); adding to each block a frame bit and a complement bit to form an intermediate word, said frame bit having a value determined in accordance with a parity of each block of M bits; determining a word digital sum (WDS) in accordance with the difference between the number of marks (logic
1) and spaces (logic
0) of said intermediate word and complement bit;determining a running digital sum (RDS) in accordance with the difference between the number of ones and zeros in the data already encoded; complementing said intermediate word in accordance with a comparison of the signs of WDS and RDS, while changing the value of said complement bit, if necessary, to indicate whether said intermediate word has been complemented or not; and combining said complement bit and said complemented intermediate word to form an output code word to be transmitted having M+2 bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An encoder for implementing a synchronous data transmission method employing an MB 1C 1F type code in which the binary data to be transmitted is divided into successive blocks each of M bits (where M is an integer) each coded by a word comprising (M+2) bits made up of the M bits of the block, complemented or not according to whether the word which would be obtained without complementing would have a word digital sum WDS equal to the difference between the number of marks (logic 1) and spaces (logic 0) of the word of the same or opposite sign as a running digital sum RDS equal to the difference between the numbers of ones and zeros in data already encoded, a complement bit C indicating whether complementing is applied or not and a frame bit complemented or not with the M bits of the block, whereby on decoding the blocks formed at the encoding stage may be reconstituted, in which method M is even and the value of the frame bit is determined according to a parity of each block of M bits, the encoder comprising:
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a demultiplexer for transforming the data to be transmitted into successive blocks of M bits, a circuit for computing the word digital sum WDS and the parity of each block connected to the output of said demultiplexer, a complementing decision circuit for comparing the signs of the word digital sum WDS and the running digital sum RDS, a circuit for computing the running digital sum RDS of the binary data already encoded on the basis of the output signal from said circuit computing the digital word sum and the output signal from said complementing decision circuit, a complementing circuit controlled by said complementing decision circuit, said complementing circuit processing the block of M bits available at the output of said demultiplexer and its parity bit delivered by said circuit computing the word digital sum and parity, and a multiplexer for transforming into an isochronous binary data bit stream the words delivered by said complementing circuit to which has been added a complement bit delivered by said complementing decision circuit. - View Dependent Claims (12)
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Specification