Methods for forming lateral and vertical DMOS transistors

• US 4,682,405 A
• Filed: 07/22/1985
• Issued: 07/28/1987
• Est. Priority Date: 07/22/1985
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A., Plummer, James D.
• Primary Examiner(s): Ozaki, George T.
• Application Number:
  US06/757,582
• Time in Patent Office: 736 Days
• Field of Search: 29/571, 29/578, 29/580, 29/576 W, 29/576 B
• US Class Current: 438/274
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A transistor is provided which includes an electrical contact (122) formed in a V-shaped groove (118). Because of the unique shape of the electrical contact, a smaller surface area is required for its formation thus rendering it possible to construct a transistor having a smaller surface area. The groove is formed by anisotropically etching an expitaxial layer (102) on a semiconductor substrate (100) using, for example, KOH.

Claims

1. A method for forming a transistor comprising the steps of:

forming a gate on a first region of semiconductor material, said first region having a first conductivity type;

forming a second region having said first conductivity type within said semiconductor material, said second region having a greater dopant concentration than the dopant concentration of said first region;

etching a groove in said semiconductor material, said groove extending through said second region, said groove having a flat bottom;

forming a third region of a second conductivity type opposite said first conductivity type within said first region but surrounding said second region, said third region extending below the bottom of said groove, at least part of said third region being formed to extend below the bottom of said groove after said step of etching said groove; and

depositing a layer of electrically conductive material in said groove, said electrically conductive material forming an electrical contact with said second and third region in said groove.

2. The method of claim 1 wherein said semiconductor material is silicon and wherein a silicon dioxide layer is formed on said second region between the time said second region is formed and the time said step of etching said groove is performed, said method further comprising the step of removing said silicon dioxide formed on said second region with a HF solution prior to the step of etching said groove.

3. The method of claim 1 wherein said gate is formed on a first surface of said semiconductor material, said method further comprising the step of forming electrically conductive material contacting said first region at said first surface, said electrically conductive material contacting said first region serving as a drain contact.

4. The method of claim 1 wherein said first, second, and third regions serve as the drain, source, and body, respectively, of said transistor.

5. The method of claim 1 wherein said transistor is a DMOS transistor.

6. A method for manufacturing a lateral transistor comprising the steps of:

forming a gate on a top surface of a first region of semiconductor material, said first region having a first conductivity type;

forming a second region having a second conductivity type within said first region, said second region extending to said top surface, said second conductivity type being opposite said first conductivity type;

forming a third region of said first conductivity type within said second region, said third region extending to said top surface;

etching a groove in said semiconductor material wherein at the conclusion of said process, said groove extends through said third region and at least part of said second region; and

depositing electrically conductive material in said groove and on at least part of said top surface of said first region, said electrically conductive material in said groove forming an electrical contact to said second and third regions, said electrically conductive material on said part of said top surface forming an electrical contact to said first region.

7. The method of claim 6 wherein said step of depositing electrically conductive material comprises the step of forming a layer of electrically conductive material extending in said groove and on said part of said top surface, said method further comprising the step of patterning said layer of electrically conductive material so that said electrically conductive material in said groove does not contact said electrically conductive material forming an electrical contact to said first region at said top surface.

8. A method of manufacturing a transistor comprising the steps of:

forming a gate on a first region of semiconductor material, said first region having a first conductivity type;

forming a second region having a second conductivity type opposite said first conductivity type within said first region;

forming a third region of said first conductivity type within said second region;

etching a groove extending through said second and third regions to said first region;

introducing additional dopants of said second conductivity type into said semiconductor material after said step of etching said groove, thereby extending said second region below the depth of said groove; and

forming a layer of electrically conductive material in said groove, said electrically conductive material electrically contacting said second and third regions at said groove.

9. The method of claim 8 wherein said first, second and third regions serve as the drain, body, and source, respectively, of said transistor.

10. A method for forming a transistor comprising the steps of:

forming a gate on a first region of semiconductor material, said first region having a first conductivity type;

forming a second region of said first conductivity type within said first region, said second region having a dopant concentration greater than the dopant concentration in said first region;

etching a groove through said second region to said first region; and

forming a third region of a second conductivity type opposite said first conductivity type after etching said groove so that the conductivity type of the semiconductor material at the bottom of said groove is changed from said first conductivity type to said second conductivity type, said third region extending to a depth below the depth of said groove, said third region surrounding said second region.

11. The method of claim 10 further comprising the step of forming electrically conductive material in said groove, said electrically conductive material serving as a source and body lead.

12. The method of claim 10 wherein said third region serves as the body of said transistor and said second region serves as the source of said transistor.