Temporal averaging using a voltage mode D/A converter

• US 4,684,922 A
• Filed: 11/17/1986
• Issued: 08/04/1987
• Est. Priority Date: 01/15/1986
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Minogue, Paschal
• Primary Examiner(s): Miller, Charles D.
• Application Number:
  US06/931,910
• Time in Patent Office: 260 Days
• Field of Search: 340/347 DA, 364/600-606, 364/572, 364/575, 364/811
• US Class Current: 341/122
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: H03H 17/04 Recursive filters

Abstract

A digitally programmable infinite impulse response (IIR) filter particularly useful as a temporal averager. The filter comprises a voltage mode multiplying digital/analog converter (12) and two sample-and-hold circuits (10, 16). The first sample-and-hold circuit receives the input signal to the system and supplies its output signal to the reference voltage input terminal of the DAC. The second sample and hold circuit has its input terminal connected to the voltage output terminal of the DAC and has its output connected to the analog ground terminal of the DAC. A digital input code (D) supplied to the DAC controls its gain and the degree of noise rejection provided by the filter, by altering the frequency response of the filter.

Claims

1. A temporal averaging circuit for supplying a filtered output from a noisy input signal applied to an input terminal thereof, comprising:

a. first and second sample-and-hold circuits;

b. a voltage-mode multiplying digital-to-analog converter (DAC) having an analog reference voltage input terminal, an analog ground terminal, an analog voltage output terminal and a digital code input port;

c. each of the sample-and-hold circuits having an input terminal, an output terminal and a terminal for receiving a sampling signal;

d. means for coupling a signal applied to the input terminal of the temporal averaging circuit from such input terminal to the input terminal of the first sample-and-hold circuit;

e. the output terminal of the first sample-and-hold circuit being connected to the analog reference voltage input terminal of the DAC;

f. the analog voltage output terminal of the DAC being connected to the input terminal of the second sample-and-hold circuit;

g. the output terminal of the second sample-and-hold circuit being connected to the analog ground terminal of the DAC; and

h. the filtered output of the circuit appearing at the analog output of the DAC.

2. The temporal averaging circuit of claim 1, wherein the gain of the DAC is controllable in response to the provision of a digital code to the digital code input port of the DAC.

3. A temporal averaging circuit for supplying a filtered output from a noisy input signal applied to an input terminal thereof, comprising:

a. first and second sample-and-hold circuits;

b. a voltage-mode multiplying digital-to-analog converter (DAC) having an analog reference voltage input terminal, an analog ground terminal, an analog voltage output terminal and a digital code input port;

c. each of the sample-and-hold circuits having an input terminal, an output terminal and a terminal for receiving a sampling signal;

d. means for coupling a signal applied to the input terminal of the temporal averaging circuit from such input terminal to the input terminal of the first sample-to-hold circuit;

e. the output terminal of the first sample-and-hold circuit being connected to one of the analog reference voltage input terminal and the analog ground terminal of the DAC;

f. the analog voltage output terminal of the DAC being connected to the input terminal of the second sample-and-hold circuit;

g. the output terminal of the second sample-and-hold circuit being connected to the other of the analog reference voltage input terminal and the analog ground terminal of the DAC; and

h. The filtered output of the circuit appearing at the analog output of the DAC.

4. The temporal averaging circuit of claim 3, wherein the gain of the DAC is controllable in response to the provision of a digital code to the digital code input port of the DAC.