Computer security device

• US 4,685,056 A
• Filed: 06/11/1985
• Issued: 08/04/1987
• Est. Priority Date: 06/11/1985
• Status: Expired due to Fees

• Current Assignee: Pueblo Technologies Incorporated
• Original Assignee: Pueblo Technologies Incorporated
• Inventors: Barnsdale, William J. Jr., Ford, Frank G.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/743,592
• Time in Patent Office: 784 Days
• Field of Search: 364/200 MS File, 178/22.08, 178/22.09
• US Class Current: 711/164
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G11C 8/20 Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access

Abstract

A computer security decide for discouraging or preventing unauthorized entry into computer systems and for preventing the unauthorized copying of proprietary computer software or data in a computer system is disclosed. The security device is based at least in part in hardware and comprises logic device means, such as a programmable logic array or a ROM, for recognizing a group of signals present on a bus indicative of unauthorized copying efforts, latch means for remembering the detection of unauthorized copying efforts, and switching device means for interrupting the flow of DC supply power to preselected components or memory locations within the computer system containing memory whose contents is to be protected to render said components or locations inaccessible. The various embodiments of the invention presented each monitor one or more buses for signals representing an unauthorized address, data or commands or sequence of addresses, data or commands indicative of either unauthorized entry into a computer system or unauthorized copying.

Claims

1. In a digital computer system having a central processing unit (CPU), at least one memory device that includes several contiguous memory locations individually definable by discrete addresses, and at least one bus forming at least part of a path for the parallel transmission of information between the CPU and memory device, a security device for preventing unauthorized access to preselected memory locations within the memory device, comprising:

logic device means external to said CPU and said memory device for recognizing a group of signals present on said bus associated with accessing at least one memory location which has been predefined as a memory location which will not intentionally be accessed during the execution of authorized programs by the CPU, and generating in response thereto a first signal;

latch means for generating and maintaining a second signal whenever the first signal has been received from said logic device means; and

switching device means, connected to the memory device, for preventing further access to at least the preselected memory locations within the memory device when the second signal is received from said latch means.

2. The security device of claim 1 wherein the memory device is fabricated as a monolithic integrated circuit and the preselected memory locations include all memory locations within the memory device and wherein the switching device means prevents access to all memory locations within the memory device by interrupting the flow of DC supply power to the memory device.

3. The security device according to claim 1 wherein:

the latch means is resettable upon occurrence of a predetermined external event; and

the switching device means restores access to the preselected memory locations when the latch means is reset.

4. The security device according to claim 1 wherein the switching device means is self-destructing when operated so that it cannot be reset.

5. The security device of claim 1 wherein the switching device will normally supply DC power to the memory device until said second signal is received from the latch means, at which time the DC power will be interrupted.

6. The security device of claim 1 wherein the switching device is normally low and is connected to the DC common of said memory device, and will remain low until said second signal is received from the latch means, at which time the switching device will go high and destructively disable the memory device.

7. The security device of claim 1 wherein said logic device means is a logic array.

8. The security device of claim 7 wherein said logic array is programmable.

9. The security device of claim 1 wherein the logic device means includes at least one NAND gate for decoding said groups of signals on said bus.

10. The security device of claim 1 wherein the logic device means includes an input for receiving an address/data enable signal, and wherein said logic device means produces the first signal only when said input is in a predetermined state.

11. The security device of claim 1 wherein the group of signals recognizable by the logic device means corresponds to an address of at least one memory location on the memory device.

12. The security device of claim 1 wherein the group of signals recognizable by the logic device means corresponds to data stored within at least one memory location on the memory device.

13. The security device of claim 1 wherein the group of signals recognizable by the logic device means corresponds to a sequence of commands transmitted along the bus for accessing the memory device.

14. The security device of claim 1 wherein the logic device means includes a read-only memory programmed with multiple addresses corresponding to memory locations on the memory device which have been picked by a random number generator means as booby-trapped addresses.

15. In a digital computer system having a central processing unit (CPU), at least one memory device provided with several contiguous memory locations therein and with at least one terminal which when enabled allows access to said memory locations and when disabled prevents access to said memory locations, and at least one bus forming at least part of a path for the parallel transmission of addresses between the CPU and memory device, a security device for deterring copying the contents of the memory device, comprising:

counter means, for monitoring a predetermined sequence of commands placed on the bus for the purpose of obtaining access to the memory device, for detecting any deviation from said predetermined sequence of commands, and generating in response to said deviation a first signal; and

switching device means, connected to said terminal of the memory device, for disabling any further access to said memory locations within said memory device upon receipt of said first signal.

16. The security device of claim 15 wherein said switching device means includes a latch circuit that remembers the first signal was present even after the first signal is no longer present, said latch circuit being resettable upon the occurrence of a preselected external event.

17. The security device of claim 15 wherein the counter means is completed of a Mealy counter circuit.

18. The security device of claim 15 wherein said switching device means includes a nonresettable element that causes said switching device to permanently disable access to the IC memory device for as long as said switching device remains connected to said IC memory device.