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High performance memory system utilizing pipelining techniques

  • US 4,685,088 A
  • Filed: 04/15/1985
  • Issued: 08/04/1987
  • Est. Priority Date: 04/15/1985
  • Status: Expired due to Term
First Claim
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1. A high performance pipelined memory system for reading data from memory in a pipelined fashion, comprising:

  • an address bus;

    a data output line;

    a memory array having rows and columns wherein one of said columns is a lock column;

    a multiplexer having a first and second input and an output;

    row selection means, connected between said address bus and said memory array, for selecting a row of data from said memory array;

    row refresh means, connected between said memory array and said multiplexer at said first input, for refreshing said requested row of data;

    column selection delay means, connected between said address bus and said multiplexer at said second input, for selecting a column from said selected row of data and for assuring that said selected column and said selected row of data arrive at their respective inputs of said multiplexer at substantially the same time,wherein a plurality of subsequent row selections and column selections can be propagated through said system before the data resulting from the first row selection and column selection appears at said output line, andwherein said lock column is for storing information that a first processor is using said selected row of data, thereby inhibiting subsequent processors from using said selected row of data until said first processor has completed using said selected row of data.

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