High performance memory system utilizing pipelining techniques

• US 4,685,088 A
• Filed: 04/15/1985
• Issued: 08/04/1987
• Est. Priority Date: 04/15/1985
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Iannucci, Robert A.
• Primary Examiner(s): Moffitt, James W.
• Assistant Examiner(s): GOSSAGE, GLENN
• Application Number:
  US06/722,920
• Time in Patent Office: 841 Days
• Field of Search: 365/230, 365/189, 365/193, 365/233, 365/194, 365/195, 364/200 MS File, 364/900 MS File
• US Class Current: 365/189.02
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A novel memory system is disclosed which utilizes pipelining techniques to read data from a memory array and to write data to a memory array. More data may be read from the novel memory system, within a unit of time, relative to the amount of data which may be read from a conventional memory system during the unit of time. The novel memory system comprises a plurality of standard elements which include a memory array, including a plurality of rows and columns, a row decoder, a row driver, column sense amplifiers, and a column multiplexer. However, the novel memory system further includes latch circuits interposed between the row decoder and the row driver, between the row driver and the memory array, between the memory array and the column sense amplifiers, and between the column sense amplifiers and the column multiplexer. The same number of latch circuits are interposed in serial fashion between the incoming row and column address bus and the column multiplexer. Consequently, as a result of the use of these latch circuits in a memory system, pipelining techniques are utilized in the memory system for the improvement of the performance of the memory system.

Claims

1. A high performance pipelined memory system for reading data from memory in a pipelined fashion, comprising:

an address bus;

a data output line;

a memory array having rows and columns wherein one of said columns is a lock column;

a multiplexer having a first and second input and an output;

row selection means, connected between said address bus and said memory array, for selecting a row of data from said memory array;

row refresh means, connected between said memory array and said multiplexer at said first input, for refreshing said requested row of data;

column selection delay means, connected between said address bus and said multiplexer at said second input, for selecting a column from said selected row of data and for assuring that said selected column and said selected row of data arrive at their respective inputs of said multiplexer at substantially the same time,

wherein a plurality of subsequent row selections and column selections can be propagated through said system before the data resulting from the first row selection and column selection appears at said output line, and

wherein said lock column is for storing information that a first processor is using said selected row of data, thereby inhibiting subsequent processors from using said selected row of data until said first processor has completed using said selected row of data.

2. The memory system of claim 1 wherein said row selection means comprises:

a first latch, connected to said address bus;

a row decoder, connected to said first latch;

a second latch, connected to said row decoder;

a driver circuit, connected to said second latch; and

a fourth latch, connected to said driver circuit.

3. The memory system of claim 2, wherein said row refresh means comprises:

a sixth latch, connected to said memory array;

a sense amplifier refresh circuit, connected to said sixth latch; and

an eighth latch, connected to said sense amplifier refresh circuit.

4. The memory system of claim 3, wherein said column selection delay means comprises:

a third latch, connected to said address bus;

a fifth latch, connected to said third latch;

a seventh latch, connected to said fifth latch; and

a ninth latch, connected to said seventh latch.

5. The memory system of claim 4, further comprising:

first clocking means for clocking said first, fourth, fifth, eighth, and ninth latches; and

second clocking means for clocking said second, third, sixth, seventh, and tenth latches.

6. A high performance pieplined memory system for writing data to memory in a pipelined fashion, comprising:

an address bus;

a data input line;

a memory array having rows and columns wherein one of said columns is a lock column;

a demultiplexer having a first and second input and an output;

row selection means, connected between said address bus and said memory array, for selecting a row of data from said memory array;

data delay means, connected between said data input line and said demultiplexer at said first input, for delaying said data to be written from arriving at said demultiplexer;

column selection delay means, connected between said address bus and said demultiplexer at said second input, for selecting a column from said selected row of data and for assuring that said selected column and said delayed data arrive at their respective inputs of said demultiplexer at substantially the same time,

wherein a plurality of susequent row selections, column selections, and data to be written can be propagated through said system before the data from said data input line is written to said selected row and said selected column of said memory array, and

wherein said lock column is for storing information that a first processor is using said selected row of data, thereby inhibiting subsequent processors from using said selected row of data.

7. A method of reading data from a memory array having rows and columns in a pipeland memory system having an address bus, a data output link and a first and second clocking means, comprising the steps of:

placing a first requested row address on said address bus and latching said first requested row address in a first latch responsive to said first clocking means;

decoding said first requested row address, latching said first requested row address in a second latch responsive to said second clocking means, placing a first requested column address on said address bus, and latching said first requested column address in a third latch also responsive to said second clocking means;

driving said first requested row address, latching said first requested row address in a fourth latch responsive to said first clocking means, latching said first requested column address in a fifth latch also responsive to said first clocking means, placing a second requested row address on said address bus, and latching said second requested row address in said first latch also responsive to said first clocking means;

retrieving first requested row data from said memory array, latching said first requested row data in a sixth latch responsive to said second clocking means, latching said first requested column address in a seventh latch also responsive to said second clocking means, placing a second requested column address on said address bus, decoding said second requested row address, latching said second requested row address in said second latch also responsive to said second clocking means, and latching said second requested column address in said third latch also responsive to said second clocking means;

sensing said first requested row data, latching said first requested row data in an eighth latch responsive to said first clocking means, latching said first requested column address in a ninth latch also responsive to said first clocking means, driving said second requested row address, latching said first requested row address in said fourth latch also responsive to said first clocking means, latching said second requested column address in said fifth latch also responsive to said first clocking means, placing a third requested row address on said address bus, and latching said third requested row address in said first latch also responsive to said first clocking means;

multiplexing said first requested row data with said first requested column address and latching the resulting data in a tenth latch responsive to said second clocking means, retrieving second requested row data from said memory array, latching said second requested row data in said sixth latch also responsive to said second clocking means, latching said second requested column address in said seventh latch also responsive to said second clocking means, placing a third requested column address on said address bus, decoding said third requested row address, latching said third requested row address in said second latch also responsive to said second clocking means, and latching said third requested column address in said third latch also responsive to said second clocking means.