Multi-layer circuit board bonding method utilizing noble metal coated surfaces

• US 4,685,210 A
• Filed: 03/13/1985
• Issued: 08/11/1987
• Est. Priority Date: 03/13/1985
• Status: Expired due to Fees

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: King, Michael M., Walter, Helen J.
• Primary Examiner(s): Goldberg, Howard N.
• Assistant Examiner(s): Arbes, Carl J.
• Application Number:
  US06/719,560
• Time in Patent Office: 881 Days
• Field of Search: 361/414, 29/852, 29/830, 29/846, 339/17 R, 339/17 M
• US Class Current: 29/830
• CPC Class Codes: H01Q 1/38 formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H05K 1/0237 High frequency adaptations H05K1/0216 takes precedence
• CPC Class Codes: H05K 1/0272 Adaptations for fluid transport, e.g. channels, holes
• CPC Class Codes: H05K 2201/015 Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
• CPC Class Codes: H05K 2201/0379 Stacked conductors
• CPC Class Codes: H05K 2201/0715 provided by an outer layer of PCB
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/0278 Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
• CPC Class Codes: H05K 3/0094 Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
• CPC Class Codes: H05K 3/328 by welding
• CPC Class Codes: H05K 3/368 parallel to each other H05K3/361 takes precedence
• CPC Class Codes: H05K 3/462 characterized by laminating only or mainly similar double-sided circuit boards
• CPC Class Codes: H05K 3/4623 the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

An electrically and mechanically sound conductive bond between layers of a multi-layer plated through hole circuit board is produced by depositing a layer of noble metal over the surfaces to be joined, juxtaposing the noble metal coated layers and subjecting them to a combination of pressure and heat for a sufficient period of time. Excellent results have been obtained in a multi-layer circuit board for a microstrip microwave antenna with 0.002 inch thick polished silver layers at bonding pressures of 490 to 575 psi and temperatures of 560 to 580 degrees F. for time periods of 20 to 30 minutes.

Claims

1. A method of forming an electrically and mechanically sound joint between internal layers of a multi-layer plated through hole printed circuit board comprising the steps of:

applying a coating of a noble metal to layer surfaces to be conductively joined on the through hole board layers;

juxtaposing the noble metal coated surfaces on the through hole board layers;

applying a layer of thermal adhesive over the outer surfaces of the juxtaposed through hole board layers;

juxtaposing imperforate outer board layers over the adhesive layers; and

exposing the juxtaposed layers to a pressure from about 100 psi to about 10,000 psi and a temperature from about 400 to about 1000 degrees F. until the noble metal coated surfaces bond to form an electrically and mechanically sound metal to metal joint and thermal adhesive is extruded into the through holes of the internal through hole board layers, thereby forming a multi-layer board with buried through hole interconnections.

2. A method according to claim 1, wherein the juxtaposed layers are subjected to heat and pressure for a time period from about 1 minute to about 24 hours.

3. A method according to claim 2, wherein said juxtaposed layers are subjected to pressure and heat for a period from about 5 minutes to about 1 hour.

4. A method according to claim 1, wherein said noble metal coating has a thickness in the range from about 0.0001 to about 0.01 inch.

5. A method according to claim 4, wherein said noble metal coating has a thickness in the range from about 0.0005 to about 0.005 inch.

6. A method according to claim 5, wherein said noble metal coating has a thickness in the range from about 0.001 to about 0.004 inch.

7. A method according to claim 1, wherein said noble metal is selected from the group consisting of silver, gold, platinum and palladium.

8. A method according to claim 6, wherein said noble metal is silver.

9. A method according to claim 1, wherein each layer of said multi-layer circuit board comprises a fiberglass reinforced polytetrafluoroethylene layer.

10. A method according to claim 9, wherein each layer of said multi-layer circuit board is copper clad.

11. A method according to claim 1, additionally comprising a step of applying a copper coating inside through holes of said circuit board layers before application of said noble metal coating, and wherein a noble metal coating is applied inside said through holes over said copper coating simultaneously with the application of said noble metal coating to the layer surfaces to be joined.

12. A method according to claim 11, wherein said copper coating is applied by plating.

13. A method according to claim 1, wherein said noble metal coating is applied by a technique selected from plating, vapor deposition, sputtering and painting.

14. A method according to claim 13, wherein said noble metal coating is applied by panel plating.

20. A method according to claim 1, wherein an electrical circuit element on one circuit board layer is electrically connected to at least one other electrical circuit element on a remote side of another circuit board layer.

21. A method acording to claim 1, comprising additional steps of masking portions of said circuit board layers prior to applying said noble metal coating and removing the masking after application of the noble metal coating.

22. A method according to claim 21, wherein said masking is effected by applying a polymeric etching resist over selected portions of said circuit board layers, and said masking is removed by subjecting the coated layers to vapor degreasing.

23. A method according to claim 1, wherein said pressure lies in the range from about 200 to about 1000 psi and said temperature lies in the range from about 450 to about 600 degrees F.

24. A method according to claim 23, wherein said pressure lies in the range from about 490 to about 575 psi and said temperature lies in the range from about 500 to about 580 degrees F.

15. A method of forming an electrically and mechanically sound joint between internal layers of a multi-layer plated through hole printed circuit board comprising the steps of:

applying a coating of silver to the layer surfaces to be joined by electroplating at a current density of from about 2 to about 10 amp/ft² for a period from about 15 minutes to about 12 hours;

juxtaposing the noble metal coated surfaces;

exposing the juxtaposed layers to a pressure from about 100 psi to about 10,000 psi and a temperature from about 400 to about 1000 degrees F. until the noble metal coated surfaces bond to form an electrically and mechanically sound metal to metal joint.

16. A method of forming an electrically and mechanically sound joint between internal layers of a multi-layer plated through hole printed circuit board comprising the steps of:

applying a coating of a noble metal to the layer surfaces to be joined;

juxtaposed the noble metal coated surfaces; and

exposing the juxtaposed layers to a pressure from about 100 psi to about 10,000 psi and a temperature from about 400 to about 1000 degrees F. until the noble metal coated surfaces bond to form an electrically and mechanically sound metal to metal joint;

wherein an adhesive is interposed between surfaces of juxtaposed circuit board layers not coated with noble metal, and an adhesive bond is formed between such layers during the exposure of the layers to pressure and heat.

17. A method according to claim 16, wherein said adhesive is a fluorinated ethylene/propylene thermoplastic adhesive.

18. A method of forming an electrically and mechanically sound joint between internal layers of a multi-layer plated through hole printed circuit board comprising the steps of:

applying a coating of a noble metal to the layer surfaces to be joined;

polishing the noble metal coating;

juxtaposing the noble metal coated surfaces; and

exposing the juxtaposed layers to a pressure from about 100 psi to about 10,000 psi and a temperature from about 400 to about 1000 degrees F. until the noble metal coated surfaces bond to form an electrically and mechanically sound metal to metal joint.

19. A method according to claim 18, wherein said polishing is effected by brushing the noble metal coated surface with a slurry of fine particles selected from the group consisting of pumice and alumina.

25. A multi-layer plated through hole printed circuit board with buried through hole interconnections produced by a process comprising the steps of:

applying a coating of a noble metal to layer surfaces to be conductively joined on the through hole board layers;

juxtaposing the noble metal coated surfaces on the through hole board layers;

applying a layer of thermal adhesive over the outer surfaces of the juxtaposed through hole board layers;

juxtaposing imperforate outer board layers over the adhesive layers; and

exposing the juxtaposed layers to a pressure from about 100 psi to about 10,000 psi and a temperature from about 400 to about 1000 degrees F. until the noble metal coated surfaces bond to form an electrically and mechanically sound metal to metal joint and thermal adhesive is extruded into the through holes of the internal through hole board layers.