Charge coupled device differencer

• US 4,686,648 A
• Filed: 12/03/1985
• Issued: 08/11/1987
• Est. Priority Date: 12/03/1985
• Status: Expired due to Term

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Fossum, Eric R.
• Primary Examiner(s): Harkcom, Gary V.
• Application Number:
  US06/805,505
• Time in Patent Office: 616 Days
• Field of Search: 364/800, 364/807, 364/861-862, 307/444, 307/607, 357/24, 365/183, 333/165, 377/60-63
• US Class Current: 257/235
• CPC Class Codes: G06G 7/14 for addition or subtraction of vector quantities G06G7/22 ; computing the average by addition; differential amplifiers H03F3/45

Abstract

A charge packet differencer is implemented in a charge coupled device in such a manner that a first charge packet may be subtracted from a second charge packet thus giving a resultant charge packet equal to the difference between the first and second charge packets. The charge coupled device differencer comprises a semiconductor substrate in which there is formed first and second charge transfer devices, first and second charge substraction mechanisms, and a charge reservoir cooperating to produce a charge packet output representative of the difference between two input charge packets using a gate charge subtraction technique.

Claims

1. A charge coupled device differencer comprising:

a semiconductor substrate (10);

first charge transfer means (12 and

     16) formed on said substrate for receiving and transferring a first quantity of charge carriers;

second charge transfer means (24 and

     28) formed on said substrate for receiving and transferring a second quantity of charge carriers;

a first charge subtraction means (34 and

     36) coupled to said first charge transfer means and responsive to said first quantity of charge carriers so as to form a first potential well in said substrate having a level determined by said first quantity of charge carriers;

second charge subtraction means (42 and

     44) coupled to said second charge transfer means and responsive to said second quantity of charge carriers so as to form a second potential well in said substrate having a level determined by said second quantity of charge carriers; and

charge reservoir means (144) for injecting a third quantity of charge carriers into said first and second potential wells and for removing a fourth quantity of charge carriers from said first and second potential wells, said fourth quantity of charge carriers being less than said third quantity of charge carriers when said first quantity of charge carriers is greater than said second quantity of charge carriers whereby the difference between said third and fourth quantity of charge carriers remains in said second potential well and represents the difference between said first and second quantity of charge carriers.

2. The charge coupled device differencer of claim 1 wherein said first charge subtraction means comprises:

a first diffusion (34) disposed in said substrate adjacent said first charge transfer means; and

a first electrode (36) overlying said substrate adjacent said charge reservoir means, said first electrode being electrically connected to said first diffusion.

3. The charge coupled device differencer of claim 2 wherein said second charge substraction means comprises:

a second diffusion (42) disposed in said substrate adjacent said second charge transfer means; and

a second electrode (44) overlying said substrate adjacent said first electrode, said second electrode being electrically connected to said second diffusion.

4. The charge coupled device differencer of claim 3 further comprising first and second precharge means (50 and 60) said first precharge means connected to said first charge subtraction means so as to place a first charge on said first electrode (36) and said second precharge means connected to said second charge subtraction means so as to place a second charge on said second electrode (44).

5. The charge coupled device differencer of claim 4 wherein said first and second precharge means comprise first and second electrical switches, said first electrical switch (50) coupled between said first electrode and a voltage source (V_O) and said second electrical switch coupled between said second electrode and said voltage source.

6. The charge coupled device differencer of claim 5 wherein said first electrical switch comprises a first transistor having its source and drain connected between said first electrode (36) and said voltage source (V_O) and said second electrical switch comprises a second transistor having its source and drain connected between said second electrode (44) and said voltage source.

7. The charge coupled device differencer of claim 3 further comprising a third charge transfer means (70 and 74) formed on said substrate adjacent said second electrode (44) for receiving and transferring said fourth quantity of charge carriers from said second electrode.

8. The charge coupled device differencer of claim 7 wherein said third charge transfer means comprises seventh (70) and eighth (74) electrodes overlying said substrate with said seventh electrode located adjacent and between said second and eighth electrodes.

9. The charge coupled device differencer of claim 1 wherein said first charge transfer means comprises:

a third electrode (12) overlying said substrate; and

a fourth electrode (16) overlying said substrate located between said third electrode and said first diffusion (34).

10. The charge coupled device differencer of claim 9 wherein said second charge transfer means comprises:

a fifth electrode (24) overlying said substrate; and

a sixth electrode (28) overlying said substrate located between said fifth electrode and said second diffusion (42).

11. The charge coupled device differencer of claim 1 wherein said charge reservoir means comprises a third diffusion (144) disposed in said substrate adjacent said first electrode (36).

12. A charge coupled device differencer comprising:

a semiconductor substrate;

first and second input electrodes overlying and insulated from said substrate, said first input electrode (12) responsive to a first clock signal (V_A) so as to form a first input potential well (116) in said substrate beneath said first input electrode, said first input potential well for holding a first charge packet (Q_A), and said second input electrode (24) responsive to a second clock signal (V_B) so as to form a second input potential well (118) in said substrate beneath said second input electrode, said second input potential well for holding a second charge packet (Q_B);

first and second charge transfer electrodes overlying and insulated from said substrate, said first charge transfer electrode (16) located adjacent said first input electrode and said second charge transfer electrode (28) located adjacent said second input electrode, said first and second charge transfer electrodes responsive to a third clock signal (V_X) so as to form a first charge transfer potential well (136) in said substrate beneath said first charge transfer electrode, said first charge transfer potential well for receiving said first charge packet (Q_A) from said first input potential well, and so as to form a second charge transfer potential well (138) in said substrate beneath said second charge transfer electrode, said second charge transfer potential well for receiving said second charge packet (Q_B) from said second input potential well;

first and second diffusions located in said substrate, said first diffusion (34) being adjacent the area below said first charge transfer electrode and said second diffusion (42) being adjacent the area below said second charge transfer electrode, said first diffusion for receiving said first charge packet (Q_A) from said first charge transfer potential well and said second diffusion for receiving said second charge packet (Q_B) from said second charge transfer potential well;

first and second charge subtractor electrodes overlying and insulated from said substrate, said first charge subtractor electrode having a first surface area (A₁) and being connected to said first diffusion, said second charge subtractor electrode having a second surface area (A₂) and being connected to said second diffusion;

first and second transistor switches each having a source connected to receive a voltage (V₀), a drain respectively connected to said first and second charge subtractor electrodes, and a gate connected to receive a fourth clock signal (V_pc) so as to place a first charge on said first charge subtractor electrode and a second charge on said second charge subtractor electrode such that a first charge subtractor potential well (128) is formed in said substrate beneath said first charge subtractor electrode and a second charge subtractor potential well (130) is formed in said substrate beneath said second charge subtractor electrode;

a third diffusion (144) located in said substrate adjacent the area below said first charge subtractor electrode, said third diffusion responsive to a fifth clock signal (V_FS) so as to fill said first and second charge subtractor potential wells (128 and

     130) with a third charge packet, then remove a portion of said third charge packet such that a fourth charge packet (Q_C) remains in said second charge subtractor potential well (130) where Q_C equals the difference between Q_A and Q_B when Q_A is greater than Q_B and said third diffusion removes the entire third charge packet from said first and second charge subtractor potential wells when Q_B is greater than Q_A ; and

first and second output electrodes overlying and insulated from said substrate, said first output electrode (70) located between and adjacent said second charge subtractor electrode and said second output electrode (74), said first output electrode being responsive to a sixth clock signal (V_XO) so as to form a first output potential well (152) in said substrate beneath said first output electrode to receive said third charge packet (Q_C) from said second charge subtractor potential well and said second output electrode being responsive to a seventh clock signal (V_ST) so as to form a second output potential well (148) in said substrate beneath said second output electrode to receive said third charge packet (Q_C) from said first output potential well.

13. The charge coupled device differencer of claim 12 wherein said substrate is p-type silicon and said first, second, and third diffusions are n+ doped silicon.

14. The charge coupled device differencer of claim 13 wherein said first and second input electrodes, said first and second charge transfer electrodes, said first and second charge subtractor electrodes, and said first and second output electrodes are insulated from said substrate by a thin insulating layer formed on said substrate between said electrodes and said substrate.

15. The charge coupled device differencer of claim 14 wherein said insulating layer is formed from silicon dioxide.

16. The charge coupled device differencer of claim 13 wherein said first and second input electrodes, said first and second charge transfer electrodes, said first and second charge subtractor electrodes, and said first and second output electrodes are formed of aluminum and polysilicon.

17. A method of subtracting a first charge packet from a second charge packet comprising the steps of:

(a) providing a semiconductor substrate having first and second charge transfer means, first and second charge subtraction means, and charge reservoir means;

(b) inputting a first charge packet into said first charge transfer means;

(c) inputting a second charge packet into said second charge transfer means;

(d) applying a voltage to said first and second charge subtraction means to respectively form first and second potential wells;

(e) transferring said first charge packet into said first charge subtraction means so as to adjust the level of said first potential well in proportion to said first charge packet;

(f) transferring said second charge packet into said second charge subtraction means so as to adjust the level of said second potential well in proportion to said second charge packet;

(g) inputting a third charge packet into said first and second potential wells by said charge reservoir means; and

(h) removing a fourth charge packet from said first and second potential wells by said charge reservoir means such that said fourth charge packet is less than said third charge packet when said first charge packet is greater than said second charge packet so that a fifth charge packet remains in said first potential well, said fifth charge packet being the difference between said third and fourth charge packets and representing the difference between said first and second charge packets.

18. The method of subtracting a first charge packet from a second charge packet of claim 17 further comprising the step of:

(a) providing said semiconductor substrate with a third charge transfer means; and

(b) transferring said fifth charge packet out of said first potential well by said third charge transfer means.