Synchronous data receiver circuit

• US 4,686,690 A
• Filed: 06/20/1985
• Issued: 08/11/1987
• Est. Priority Date: 06/22/1984
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Sato, Osamu
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Huseman, M.
• Application Number:
  US06/746,700
• Time in Patent Office: 782 Days
• Field of Search: 375/108, 375/114, 375/116, 375/118, 375/88, 370/105, 370/108,100, 371/5, 371/47-51
• US Class Current: 375/365
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15
• CPC Class Codes: H04L 7/046 using a dotting sequence
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

The synchronous data receiver circuit, after temporarily storing received data in a data memory having a large enough capacity to store at least two frames, detects a frame synchronization signal pattern with a pattern match circuit, then stores the message data alone of the received data in a data buffer, detects errors with a decoder and checks whether the detected frame synchronization signal pattern is the correct pattern of the frame synchronization signal or a wrong frame synchronization signal pattern contained in the message data. If it is the correct frame synchronization signal, the message data is sent to a data processing unit at the next stage or, if it is a wrong frame synchronization signal pattern, the frame synchronization signal pattern is checked again from the next data on.

Claims

1. A synchronous data receiver circuit comprising:

serial/parallel converter means for converting serial data, comprising at least frame synchronization data and message data, into parallel data;

data memory means for storing at least two frames of the parallel data supplied from said serial/parallel converter means;

pattern matching detector means for detecting in the patterns of the data stored in said data memory means a frame synchronization signal;

data buffer means for storing, as message data, data of a prescribed bit length after the data detected as the frame synchronization signal by said pattern matching detector means;

decoder means for detecting errors in the message data stored in said data buffer means; and

control means for supplying, when the number of errors detected by said decoder means is smaller than a prescribed number, the message data stored in said data buffer means to a data processing circuit or, when the number of errors detected by said decoder means is equal to or greater than said prescribed number, causing pattern matching to be performed again beginning with the data next to the frame synchronization signal earlier detected by said pattern matching detector means.

2. A synchronous data receiver circuit, as claimed in claim 1, wherein said serial/parallel converter means converts said serial data into eight-bit parallel data.

3. A synchronous data receiver circuit, as claimed in claim 1, wherein said decoder means detects and corrects errors.

4. A synchronous data receiver circuit, as claimed in claim 1, wherein said control means is comprised of a microprocessor.

5. A synchronous data receiving method comprising the following steps:

a. converting serial data into parallel data;

b. storing said parallel data in data memory;

c. detecting in the patterns of the data stored in the data memory a frame synchronization signal;

d. storing in a data buffer, as message data, data of a prescribed bit length after the patterns of data are matched with the frame synchronization signal;

e. detecting errors in the message data stored in the data buffer;

f. supplying, when the number of errors detected is smaller than a prescribed number, the message data stored in the data buffer for data processing at a later stage; and

g. causing, when the number of errors detected is equal to or greater than said prescribed number, pattern matching to be performed again beginning with the data next to the frame synchronization signal earlier detected.

6. A synchronous data receiving method, as claimed in claim 5, wherein said serial data are converted into eight-bit parallel data.

7. A synchronous data receiving method, as claimed in claim 5, wherein at said error detectin step errors are also corrected.