Hierarchical configurable gate array

• US 4,688,072 A
• Filed: 07/07/1986
• Issued: 08/18/1987
• Est. Priority Date: 06/29/1984
• Status: Expired due to Term

• Current Assignee: Hughes Aircraft Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Block, Jay M., Heath, Herbert E.
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): Limanek, Robert P.
• Application Number:
  US06/882,446
• Time in Patent Office: 407 Days
• Field of Search: 357/45, 357/40, 357/70, 357/68, 364/491
• US Class Current: 257/202
• CPC Class Codes: H01L 27/11807 CMOS gate arrays

Abstract

A hierarchical configurable gate array is disclosed and includes a plurality of cluster regions (10,20,30,40) arranged in different levels. The first level cluster (10) includes an integral number N multi-terminal components for providing canonical functions. The second level cluster (20) includes N first level clusters; and higher level clusters (30,40) each includes N clusters of the next lower level. Interconnect regions (13,15,17,19) are provided within each cluster for interconnections between the N elements of each level. Selected input or output ports for each element of a cluster are available for interconnection at more than one location.

Claims

1. An hierarchical gate array comprising:

at least three clusters of increasing level and size, each cluster having logic gates grouped in a plurality of cluster elements where the number of gates in a cluster increases with cluster level;

respective interconnect regions within each cluster for accommodating selected interconnections between cluster elements, said selected interconnections defining respective cluster functions for each said cluster and said interconnect regions having respective areas related to the respective number of gates in respective clusters;

respective input/output means located about the periphery of each cluster for providing access to the cluster functions of respective cluster regions; and

wherein each higher level cluster above the first level cluster includes as its cluster elements a plurality of lower level clusters separated by a respective interconnect region which accommodates interconnections between the respective input/output means of said lower level clusters.

2. The hierarchical gate array of claim 1 wherein each said respective input/output means provides access to its associated cluster functions at more than one location on the periphery of its associated cluster, whereby said cluster functions that are available at more than one locations are considered to be multiported.

3. The hierarchical gate array of claim 2 wherein each said cluster includes four cluster elements and occupies a four-sided region, and wherein said interconnect area is of a cruciform shape and separates said four cluster elements.

4. The hierarchical gate array of claim 3 wherein said multiported cluster function are available on opposite sides of respective clusters.

5. The hierarchical gate array of claim 1 wherein said interconnect regions have respective configurations which are unaffected by the specific technology used in fabricating said cluster elements.

6. An hierarchical gate array comprising:

a plurality of first level clusters each having four logic gates as first level cluster elements, said elements of each first level cluster being arranged in a four-sided region and separated by a first level interconnect region within said four-sided region;

a plurality of second level clusters each having four of said first level clusters as second level cluster elements, said elements of each second level cluster being arranged in a second level four-sided region and separated by a second level interconnect region within said second level four-sided region;

a third level cluster having four of said second level clusters as third level cluster elements, said elements being arranged in a third level four-sided region and separated by a third level interconnect region within said third level four-sided region;

said first, second and third level interconnect regions for respectively accommodating selected interconnections between cluster elements of respective clusters which define respective cluster functions for each cluster, and having respective areas related to the respective number of gates in respective clusters; and

respective input/output means for each of said first, second, and third level clusters for respectively providing access to cluster functions of respective cluster regions.

7. The hierarchical gate array of claim 6 wherein each said respective input/output means provides access to its associated cluster functions at more than one location on the periphery of its associated cluster, whereby said cluster functions that are available at more than one locations are considered to be multiported.

8. The hierarchical gate array of claim 7 wherein each said interconnect area is of a cruciform shape and separates said four cluster elements.

9. The hierarchical gate array of claim 8 wherein said multiported cluster functions are available on opposite sides of respective clusters.

10. The hierarchical gate array of claim 6 wherein said interconnect regions have respective configurations which are unaffected by the specific technology used in fabricating said cluster elements.