High speed data transfer method and apparatus

• US 4,688,168 A
• Filed: 08/23/1984
• Issued: 08/18/1987
• Est. Priority Date: 08/23/1984
• Status: Expired due to Fees

• Current Assignee: Picker International, Inc. (Koninklijke Philips N.V.)
• Original Assignee: Picker International, Inc. (Koninklijke Philips N.V.)
• Inventors: McCaskey, John P., Gudaitis, Donald A., Hostetler, Michael S.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Lacasse, Randy W.
• Application Number:
  US06/644,023
• Time in Patent Office: 1,090 Days
• Field of Search: 364/200, 364/900, 364/134
• US Class Current: 710/107
• CPC Class Codes: G06F 13/362 with centralised access control

Abstract

A high speed data transfer method and apparatus. A high speed data bus includes separate data transfer and master control bus portions. A system host computer loads a sequence of source and destination addresses corresponding to communications units coupled to the bus into memory in a bus master controller. The bus controller sequences through these address pairs at an aggregate rate greater than at least some of the devices'"'"' ability to transfer data to enhance data transmission speed on the bus. Bus cycles are allocated to devices on the bus according to a scheme dependent on those devices ability to utilize the bus. High speed devices are allocated a greater number of bus cycles per unit time than slower devices.

Claims

1. A data communication system for transferring data at an enhanced data transfer rate comprising:

(a) a dual transmission bus, said bus having a data portion for the transmission of digital data messages and a control portion for allocating the transmission of data messages on the bus data portion;

(b) a plurality of communications units coupled to the transmission bus, each of said communications units including a data interface coupled to the data portion of said transmission bus;

(c) a bus controller for coordinating data transmission on the bus between said communications units;

said bus controller including (i) address control means having an address input coupled to the control portion of said bus and an address output coupled to said bus data portion for presenting source and destination addresses on the data portion of the bus;

said address control means organized into one or more data transfer groups wherein each one of said data transfer groups includes multiple source and destination pairs, said source and destination pairs organized within a group to interleave data transfers between communications units within a transfer group to achieve a data transmission bandwidth greater than the maximum continuous data transfer bandwidth of one or more of the communication units in the transfer group; and

(ii) means for allocating bus cycles to the data transfer groups within the address control means; and

(d) programming means coupled to the control portion of the bus for transmitting said multiple source and destination pairs to said address control means.

2. The data processing apparatus of claim 1 wherein the means for allocating comprises mean for skipping a data transfer within a transfer group in response to a status signal from one of the communications units indicating said one unit is not ready to participate in a data transfer.

3. The data communication system of claim 1 wherein each of said communications units has an associated controller to coordinate the sending or receiving of data to or from said data portion in response to the receipt of one of said source or destination addresses on said data portion.

4. The data communications system of claim 1 wherein said means for allocating includes (i) logic means coupled to the data portion of said bus for determining an active transfer group in response to a signal on the data portion from one of said communications units (ii) an allocation table coupled to the control portion of the bus to store bus cycle allocations from the programming means;

and (iii) decoder means coupled to the logic means and the allocation table to index into the address control means and cause said address control means to present source and destination addresses from an active transfer group to the address output.

5. The data communications system of claim 4 wherein the data portion of said bus comprises a group disable line corresponding to each transfer group and wherein each group disable line is tested by the logic means in determining an active transfer group.

6. The communications system of claim 1 wherein one or more of said comnunication units form a source of digital imaging data, said imaging data corresponding to discrete regions of an image;

and wherein one or more of said communications units form an imaging device for displaying an image generated from said digital imaging data.

7. A method for allocating transfers between a plurality of communications units coupled to a data transfer path comprising the steps of:

assigning a first set of communications units to multiple source and destination address pairs to form a first data transfer group;

assigning a different set of multiple communication unit source and address pairs to one or more additional data transfer groups;

allocating each said data transfer group one or more cycles on the transfer path;

determining an active group and directing a data transfer for a source/destination pair in said active group by presenting source and address pair information on the data transfer path;

counting said transfer and comparing said count to the number of cycles allocated for said active group; and

,

redetermining an active data transfer group based upon said comparison and a monitoring of the status of said transfer path and directing further data transfers between communications units of an active data transfer group.

8. The method for allocating transfers of claim 7 where the assigning steps organize successive transfers to originate or end at multiple communications units communicating with a single or multiple other communications unit(s) to interleave data transfers within a group thereby achieving a transfer rate greater than a transfer rate of at least one of said multiple communications units.

9. The method of claim 7 wherein at least one set of said communications units assigned to a transfer group comprises an imaging device and multiple storage devices for storing image data and the multiple source and destination pairs are interleaved to cause data to be transferred to the imaging device at a rate faster than the maximum data processing speed of the multiple storage devices.

10. A bus allocation controller for directing a sequence of data transfers between pairs of communications units coupled to a data bus comprising:

a memory unit organized into independent data transfer groups of source and destination device pair designations;

interface means for coupling a selected one of said source and destination pair designations to said bus to apprise a source and destination communications unit corresponding to the source and destination device pair designation to transfer data on the data bus;

controller means for programming the series of source and destination pairs in the memory unit to achieve a data transmission bandwidth greater than the maximum continuous data transfer bandwidths of said source and destination devices within each independent data transfer group; and

group allocation means coupled to the memory unit to allocate bus cycles between said independent data groups on a shared basis.