Control of data access to memory for improved video system
First Claim
Patent Images
1. A dual-port memory device, comprising:
- an array of memory cells;
address terminals;
a data input terminal;
a data output terminal;
means, responsive to address signals received by said address terminals, for addressing a memory cell in said array;
random input means for writing data received by said data input terminal to the memory cell addressed by said addressing means;
random output means for presenting the contents of the memory cell addressed by said addressing means to said data output terminal;
a register comprised of a plurality of memory cells;
a transfer control terminal;
a serial clock terminal;
means, coupled to said array and to said register, for transferring the contents of a plurality of memory cells in said array into memory cells in said register, said transfer occurring responsive to a transfer signal received by said transfer control terminal;
a serial output terminal;
serial output means, connected to a memory cell in said register and to said serial output terminal, for communicating to said serial output terminal the contents of said memory cell in said register connected thereto; and
means, responsive to a shift signal received by said serial clock terminal, for shifting the contents of another memory cell in said register to said serial output means so that, responsive to a series of said shift signals received by said serial clock terminal, the contents of a series of memory cells in said register are communicated to said serial output terminal;
wherein said transferring means is disabled after said contents of said plurality of memory cells in said array are transferred into said register, so that said random input means and said random output means may write and present, respectively, the contents of memory cells in said array addressed by said addressing means independently from said serial output means communicating the contents of a series of said memory cells in said register to said serial output terminal;
and wherein said serial output means communicates the contents of said memory cell in said register connected thereto to said serial output means after a transfer by said transfer means and prior to the first shift signal received by said serial clock means after said transfer by said transfer means.
1 Assignment
0 Petitions
Accused Products
Abstract
In a video computer system having a RAM chip with a shift register connected to its serial output terminal and actuated by a first clock circuit, a second different clock circuit is included to cause the data bit in the first stage of the register to also appear at the serial output terminal of the chip. Accordingly, signals from the first clock circuit will then sequentially transfer data bits from the shift register, to the output terminal of the RAM chip, without omitting or losing a clock cycle, or a portion thereof.
-
Citations
15 Claims
-
1. A dual-port memory device, comprising:
-
an array of memory cells; address terminals; a data input terminal; a data output terminal; means, responsive to address signals received by said address terminals, for addressing a memory cell in said array; random input means for writing data received by said data input terminal to the memory cell addressed by said addressing means; random output means for presenting the contents of the memory cell addressed by said addressing means to said data output terminal; a register comprised of a plurality of memory cells; a transfer control terminal; a serial clock terminal; means, coupled to said array and to said register, for transferring the contents of a plurality of memory cells in said array into memory cells in said register, said transfer occurring responsive to a transfer signal received by said transfer control terminal; a serial output terminal; serial output means, connected to a memory cell in said register and to said serial output terminal, for communicating to said serial output terminal the contents of said memory cell in said register connected thereto; and means, responsive to a shift signal received by said serial clock terminal, for shifting the contents of another memory cell in said register to said serial output means so that, responsive to a series of said shift signals received by said serial clock terminal, the contents of a series of memory cells in said register are communicated to said serial output terminal; wherein said transferring means is disabled after said contents of said plurality of memory cells in said array are transferred into said register, so that said random input means and said random output means may write and present, respectively, the contents of memory cells in said array addressed by said addressing means independently from said serial output means communicating the contents of a series of said memory cells in said register to said serial output terminal; and wherein said serial output means communicates the contents of said memory cell in said register connected thereto to said serial output means after a transfer by said transfer means and prior to the first shift signal received by said serial clock means after said transfer by said transfer means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A data processing system, comprising:
-
a microprocessor; bus means, connected to said microprocessor, for carrying data signals, control signals, and address signals; utilization means, having a serial input, for utilizing data processed by said microprocessor; and memory means, connected to said bus means, for storing data, said memory means comprising; an array of memory cells; means, responsive to address signals presented by said microprocessor on said bus means, for addressing a memory cell in said array; random data input means for writing data presented by said microprocessor on said bus means to the memory cell addressed by said addressing means; random output means for presenting onto said bus means the contents memory cell addressed by said addressing means; a register comprised of a plurality of memory cells; means, coupled to said array and to said register, for transferring the contents of a plurality of memory cells in said array into memory cells in said register, said transfer occurring responsive to a transfer control signal presented by said microprocessor on said bus means; serial output means, connected to a memory cell in said register and to said serial input of said utilization means, for communicating to said utilization means the contents of said memory cell in said register connected thereto; and means, responsive to a shift control signal on said bus means, for shifting the contents of another memory cell in said register to said serial output means so that, responsive to a series of said shift control signals, the contents of a series of memory cells in said register are communicated to said utilization means; wherein said transferring means is disabled after said contents of said plurality of memory cells in said array are transferred into said register, so that said microprocessor may write and read the contents of memory cells in said array corresponding to addresses it presents to said bus means, independently from said serial output means communicating the contents of a series of said memory cells in said register to said utilization means; and wherein said serial output means communicates the contents of said memory cell in said register connected thereto to said utilization means after a transfer by said transfer means and prior to said shifting means receiving said shift control signal on said bus means. - View Dependent Claims (10, 11, 12, 13, 14, 15)
-
Specification