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Control of data access to memory for improved video system

  • US 4,688,197 A
  • Filed: 12/30/1983
  • Issued: 08/18/1987
  • Est. Priority Date: 12/30/1983
  • Status: Expired due to Term
First Claim
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1. A dual-port memory device, comprising:

  • an array of memory cells;

    address terminals;

    a data input terminal;

    a data output terminal;

    means, responsive to address signals received by said address terminals, for addressing a memory cell in said array;

    random input means for writing data received by said data input terminal to the memory cell addressed by said addressing means;

    random output means for presenting the contents of the memory cell addressed by said addressing means to said data output terminal;

    a register comprised of a plurality of memory cells;

    a transfer control terminal;

    a serial clock terminal;

    means, coupled to said array and to said register, for transferring the contents of a plurality of memory cells in said array into memory cells in said register, said transfer occurring responsive to a transfer signal received by said transfer control terminal;

    a serial output terminal;

    serial output means, connected to a memory cell in said register and to said serial output terminal, for communicating to said serial output terminal the contents of said memory cell in said register connected thereto; and

    means, responsive to a shift signal received by said serial clock terminal, for shifting the contents of another memory cell in said register to said serial output means so that, responsive to a series of said shift signals received by said serial clock terminal, the contents of a series of memory cells in said register are communicated to said serial output terminal;

    wherein said transferring means is disabled after said contents of said plurality of memory cells in said array are transferred into said register, so that said random input means and said random output means may write and present, respectively, the contents of memory cells in said array addressed by said addressing means independently from said serial output means communicating the contents of a series of said memory cells in said register to said serial output terminal;

    and wherein said serial output means communicates the contents of said memory cell in said register connected thereto to said serial output means after a transfer by said transfer means and prior to the first shift signal received by said serial clock means after said transfer by said transfer means.

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