Time division exchange for carrying out a loop-back test

• US 4,688,208 A
• Filed: 08/12/1985
• Issued: 08/18/1987
• Est. Priority Date: 08/15/1984
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kawaguchi, Tomohiro
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Kuntz, Curtis
• Application Number:
  US06/764,583
• Time in Patent Office: 736 Days
• Field of Search: 370/15, 370/85, 370/16, 370/68, 370/67, 379/5, 371/11, 371/22, 371/31
• US Class Current: 370/249
• CPC Class Codes: H04M 3/244 for multiplex systems
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence
• CPC Class Codes: H04Q 2213/13103 Memory
• CPC Class Codes: H04Q 2213/1316 Service observation, testing
• CPC Class Codes: H04Q 2213/13292 Time division multiplexing, TDM

Abstract

A time division exchange interchanges predetermined time slots of a time division multiplexed signal and returns it to a network during a loop-back test. A buffer memory in a time division multiplexed trunk is used to interchange the predetermined time slots. Alternatively, the buffer memory is provided in a return loop for use during the loop-back test. Therefore, it can be determined that the received signal is sent from another exchange and the loop-back test can be performed using ordinary exchanging processing procedures.

Claims

1. A time division exchange for serving plural lines, comprising:

a network, coupled to the lines, for transmitting and receiving time division multiplexed signals;

a time division multiplexed trunk, coupled to said network, for providing, as an output time division multiplexed signal to another exchange, the time division multiplexed signal transmitted by said network, and for providing an input time division multiplexed signal to said network as the received time division multiplexed signal, said time division multiplexed trunk including means for interchanging predetermined time slots in one of the time division multiplexed signals when a loop-back test is to be performed; and

return means, coupled to said time division multiplexed trunk, for receiving the output time division multiplexed signal and for returning it to said time division multiplexed trunk, as the input time division multiplexed signal, during the loop-back test.

2. A time division exchange according to claim 1, wherein said interchanging means comprises a buffer memory circuit for interchanging the predetermined time slots.

3. A time division exchange according to claim 2, wherein said buffer memory circuit includes a buffer memory for storing data, and means for interchanging the order in which the information in the predetermined time slots is read out of the buffer memory.

4. A time division exchange according to claim 1, further comprising:

an upstream highway having plural lines for connecting said network and said time division multiplexed trunk; and

a downstream highway having plural lines for connecting said network and said time division multiplexed trunk.

5. A time division exchange for serving plural lines, comprising:

a network, coupled to the lines, for transmitting and receiving time division multiplexed signals;

a time division multiplexed trunk, coupled to said network, for providing, as an output time division multiplexed signal to another exchange, the time division multiplexed signal transmitted by said network, and for providing an input time division multiplexed signal; and

return means, coupled to said time division multiplexed trunk, for interchanging predetermined time slots of the output time division multiplexed signal and for returning the input time division multiplexed signal having interchanged time slots to said time division multiplexed trunk during a loop-back test, said time division multiplexed trunk providing the input time division multiplexed signal having the interchanged time slots to said network as the received time division multiplexed signal.

6. A time division exchange according to claim 5, further comprising:

an upstream highway having plural lines for connecting said network and said time division multiplexed trunk; and

a downstream highway having plural lines for connecting said network and said time division multiplexed trunk.

7. A time division exchange according to claim 5, wherein said return means includes a buffer memory circuit for interchanging the predetermined time slots.

8. A time division exchange according to claim 7, wherein said buffer memory circuit includes a buffer memory for storing data, and means for interchanging the reading order of the data stored in the buffer memory.

9. A time division exchange, connected to at least one other exchange, for serving plural lines, comprising:

a network, coupled to the lines, for transmitting a first time division multiplexed signal and for receiving a second time division multiplexed signal;

a time division multiplexed trunk, coupled to said network and to another exchange, for receiving the first time division multiplexed signal and for providing a third time division multiplexed signal as an output to the other exchange, said time division multiplexed trunk receiving a fourth time division multiplexed signal from the other exchange and for providing the second time division multiplexed signal to said network, said time division multiplexed trunk including means for interchanging predetermined time slots in one of the time division multiplexed signals when a loop-back test is to be performed; and

return means, coupled to said time division multiplexed trunk, for receiving the third time division multiplexed signal and for returning the third time division multiplexed signal to said time division multiplexed trunk, as the fourth time division multiplexed signal, during the loop-back test.

10. A time division exchange according to claim 9, wherein said interchanging means comprises a buffer memory circuit for interchanging the predetermined time slots.

11. A time division exchange according to claim 10, wherein said buffer memory circuit includes a buffer memory for storing data, and means for interchanging the order in which the information in the predetermined time slots is read out of the buffer memory.

12. A time division exchange according to claim 9, further comprising:

an upstream highway having plural lines for connecting said network and said time division multiplexed trunk; and

a downstream highway having plural lines for connecting said network and said time division multiplexed trunk.

13. A time division exchange according to claim 9, wherein said time division multiplexed trunk comprises:

first buffer means for receiving the first time division multiplexed signal and for outputting the third time division multiplexed signal; and

second buffer means for receiving the fourth time division multiplexed signal and for outputting the second time division multiplexed signal to said network.

14. A time division exchange according to claim 13, wherein said first buffer means includes said means for interchanging predetermined time slots in the first time division multiplexed signal when a loop-back test is to be performed.

15. A time division exchange according to claim 14, wherein said first buffer means comprises:

a buffer memory for receiving and storing the first time division multiplexed signal;

a read control memory connected to said buffer memory, said read control memory having a first portion for providing a read address for reading data from said buffer memory during an ordinary switching process and having a second portion for providing a read address for reading data from said buffer memory during the loop-back test; and

switching means for selecting one of the first and second portions of said read control memory to provide the read address for reading data from said buffer memory as the third address for reading data from said buffer memory as the third time division multiplexed signal.

16. A time division exchange according to claim 13, wherein said second buffer means includes said means for interchanging predetermined time slots in the fourth time division multiplexed signal when a loop-back test is to be performed.

17. A time division exchange according to claim 16, wherein said second buffer means comprises:

a buffer memory for receiving and storing the fourth time division multiplexed signal;

a read control memory connected to said buffer memory, said read control memory having a first portion for providing a read address for reading data from said buffer memory during an ordinary switching process and having a second portion for providing a read address for reading data from said buffer memory during the loop-back test; and

switching means, connected to said read control memory, for selecting one of the first and second portions of said read control memory to provide the read address for reading data from said buffer memory as the second time division multiplexed signal.