Test apparatus for electronic control systems, particularly automotive-type computers

• US 4,689,554 A
• Filed: 09/04/1985
• Issued: 08/25/1987
• Est. Priority Date: 10/10/1984
• Status: Expired due to Fees

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Schneider, Erich, Schnaibel, Eberhard
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Burns, W.
• Application Number:
  US06/772,724
• Time in Patent Office: 720 Days
• Field of Search: 178/69 G, 324/73 R, 324/158 R, 329/106, 340/353, 340/792, 340/814, 375/22
• US Class Current: 324/73.1
• CPC Class Codes: G07C 5/0808 Diagnosing performance data testing of vehicles G01M17/00; testing of electrical installation on vehicles G01R31/005

Abstract

To provide an inexpensive test apparatus for testing the performance of control computers in automotive vehicles, for example sufficiently simple to be affordable by gasoline service stations, small garages and the like, a shift register-memory combination unit is provided receiving the data in serial, preferably Pulse-Duration-Modulated (PDM), form, and a monostable flip-flop is connected to the shift register, connected to be SET by a flank, preferably the trailing flank, of the first bit of a data word, and having a timing period somewhat longer than the longest interval between sequential bits, the monostable flip-flop being connected to control the shift register to transfer data in the shift register to a memory section thereof for simultaneous display of the data in the various storage locations of the memory section of the shift register. A counter can be used to inhibit application of clock pulses to the shift register beyond a predetermined count so that only those data which have been transmitted up to the inhibit count will be stored in the shift register for subsequent display.

Claims

1. Test apparatus, for testing electronic control systems providing clock signals and test data words as a combined serial data stream, having

a serial data input port (1);

a display device (6);

and comprising, in accordance with the invention,

a combination shift-register-and-memory unit (5) having a clock input (Cl) and a data input (D) connected to the serial data input port (1) for receiving and reading data, and for storing data;

means (4), connected between said serial data input port (1) of said test apparatus and said data input (D) of said combination unit (5), for separating said combined serial data stream into clock signals and test data in the form of a sequence of logical zero and logical one signals,

said means (4) applying said test data to said data input (D) for sequential shifting thereof, in synchronism with said clock signals, into a shift register portion of said combination unit;

a retriggerable monostable flip-flop (3) which is connected to receive said test data and has a timing period selected to detect the end of each data word and thereby recognize termination of data transmission to the shift-register-and-memory unit (5),

the monostable flip-flop (3) having an output coupled to an input of the shift register other than said data input (D) and controlling the shift-register-and-memory unit (5) to transfer shifted data from said shift register portion of said combination unit (5) into a memory portion thereof and to display the data stored in the memory portion.

2. Test apparatus according to claim 1, wherein the monostable flip-flop (3) has a timing period which is longer than the longest gap, between sequential bits of serial data, expected to be applied to the input port to reliably recognize termination of a data word applied to the serial data input port.

3. Test apparatus according to claim 1, wherein said means for separating and applying comprises a low-pass filter means (4) connected to the data input (D) of the combination shift-register-and-memory unit (5).

4. Test apparatus according to claim 1, further including a controllable counter (8) connected to the output of the monostable flip-flop (3) to be SET thereby, the counter changing counter state in accordance with a clock rate of the data words applied to the input port (1),

said counter providing a count output signal (CO) at a predetermined count state,

and means for connecting the count output signal to the shift register, said means suppressing further application of clock pulses to the combination shift register--memory unit (5).

5. Test apparatus according to claim 4, wherein said connection means comprises a diode (10) coupled to the clock input of the shift register--memory unit combination (5) and connected by the count output of the counter (CO) to connect the clock input of the combination shift register--memory output unit to a reference voltage.

6. Test apparatus according to claim 1, further including a noise or stray pulse suppression filter (2) connected serially to the data input port (1).

7. Test apparatus for combination with control apparatus for controlling functions in an automotive vehicle, said control apparatus providing data in serial form,

said test apparatus comprising the apparatus claimed in claim 1, and said data in serial form being connected to the serial data input port (1).

8. Test apparatus according to claim 1, wherein said combined data stream is a train of self-clocked digital pulses,

an output of said means (4) for separating is a voltage signal whose level depends upon the duration of the most recent pulse, and

said clock input of said combination unit (5) is responsive to a flank of each pulse is said pulse train.

9. Test apparatus according to claim 8, wherein said means (4) for separating comprises a resistor and a capacitor in series.

10. Test apparatus according to claim 3, wherein said low-pass filter means (4) comprises a resistor and a capacitor in series.

11. Test apparatus according to claim 1, wherein said combination unit (5) has a strobe input (St) and the output of said monostable flip-flop (3) is connected thereto.