Two-wire bus-system comprising a clock wire and a data wire for interconnecting a number of stations

• US 4,689,740 A
• Filed: 11/02/1981
• Issued: 08/25/1987
• Est. Priority Date: 10/31/1980
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Moelands, Adrianus P. M. M., Schutte, Herman
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Eakman, Christina M.
• Application Number:
  US06/317,693
• Time in Patent Office: 2,122 Days
• Field of Search: 364/200, 364/900, 375/36, 375/95, 375/117, 375/106, 340/825.50, 340/825.51, 370/48, 370/85, 370/89
• US Class Current: 713/600
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A computer system comprises a number of stations which are interconnected by means of a clock bus wire (20) and a data bus wire (22) which both form a wired logic function of the signals generated thereon by the stations (32, 34). During the clock pulses, the signal on the data bus wire is stationary; it may change between the clock pulses. Start and stop conditions are formed by a signal combination between clock bus wire and data bus wire (60 and 62, respectively) which is not permissible in a data stream. If there is more than one master station so that a composite clock signal occurs on the clock bus wire, the clocks of the relevant master stations are each time resynchronized to the actual transitions in the composite clock signal.

Claims

1. A system for data transmission comprising:

(A) at least one master transmitting station which is capable of controlling data transmission, comprising;

(a) a clock terminal;

(b) a data terminal;

(c) means for producing a clock signal at the clock terminal by allowing the clock terminal to assume a second voltage level for each of a series of periodic clock pulse intervals and by forcing the clock terminal to a first voltage level at all other times during production of the clock signal;

(d) means for producing a start signal which indicates that the master station is prepared to control data transmission by allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;

(e) means for producing a stop signal which indicates that the master station has finished controlling data transmission by forcing the voltage level at the data terminal to the first voltage level during a first fraction of a clock pulse interval and then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval;

(f) means for transmitting binary data by forcing the voltage at the data terminal to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage at the data terminal to assume the second voltage level during an entire clock pulse interval to transmit a second data value; and

(g) at least all but one of the master transmitting stations further comprising means for establishing priority when a plurality of master stations simultaneously attempt to control data transmission which detect the voltage level at the data terminal and which cause the master station which contains said means for establishing priority to cease attempted control of data transmission by allowing the data terminal and the clock terminal to assume the second voltage level for at least a predetermined interval after detection of the first voltage level during a clock interval in which that master station has allowed the data terminal to assume the second voltage level;

(B) at least one receiving station comprising a data terminal and a clock terminal;

(C) a data bus which interconnects the data terminals of all the stations;

(D) a clock bus which interconnects the clock terminals of all the stations; and

(E) means which maintain the buses at the second voltage level in the absence of forcing by the stations.

2. The system of claim 1 comprising at least two of said master transmitting stations.

3. The system of claims 1 or 2 wherein the means for producing a clock signal comprises:

a time slot generator which produces a periodic clock signal at the clock terminal by first forcing the clock terminal to the first voltage level for a first interval of predetermined duration, by then allowing the clock terminal to assume the second voltage level for a second interval of predetermined duration, and by then again forcing the clock terminal to the first voltage level; and

means which detect the voltage level at the clock terminal and which cause the time slot generator to start the first interval whenever the voltage level at the clock terminal changes from the second voltage level to the first voltage level;

whereby a synchronous clock signal will be produced on the clock bus by simultaneously operating master transmitting stations.

22. The system of claim 1, 9, 10, 11 or 21 wherein each bus is a single wire.

4. A data transmission station comprising:

(a) a clock terminal;

(b) a data terminal;

(c) means for producing a clock signal at the clock terminal by allowing the clock terminal to assume a second voltage level for each of a series of periodic clock pulse intervals and by forcing the clock terminal to a first voltage level at all other times during production of the clock signal;

(d) means for producing a start signal which indicates that the station is prepared to transmit data by allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;

(e) means for producing a stop signal which indicates that the station has finished transmitting data by forcing the voltage level at the data terminal to the first voltage level during a first fraction of a clock pulse interval and then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval; and

(f) means for transmitting binary data by forcing the voltage at the data terminal to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage at the data terminal to assume the second voltage level during an entire clock pulse interval to transmit a second data value.

5. The data transmission station of claim 4 wherein by means for producing a clock signal comprises:

a time slot generator which produces a periodic clock signal at the clock terminal by first forcing the clock terminal to a first voltage level for a first interval of predetermined duration, by then allowing the clock terminal to assume a second voltage level for a second interval of predetermined duration, and by then again forcing the clock terminal to the first voltage level, and

means which detect the voltage level at the clock terminal and which cause the time slot generator to start the first interval whenever the voltage level at the clock terminal changes from the second voltage level to the first voltage level.

6. A data transmission system comprising:

at least two of the data transmission stations of claim 5;

a clock bus which interconnects the clock terminals of the stations; and

means which maintains the clock bus at the second voltage level in the absence of forcing by the data transmission stations.

7. In a station for data transmission, the improvement comprising:

a clock terminal;

a time slot generator which produces a periodic clock signal at the clock terminal by first forcing the clock terminal to a first voltage level for a first interval of predetermined duration, by then allowing the clock terminal to assume a second voltage level for a second interval of predetermined duration, and by then again forcing the clock terminal to the first voltage level, and

means which detect the voltage level at the clock terminal and which cause the time slot generator to start the first interval whenever the voltage level at the clock terminal changes from the second voltage to the first voltage level.

8. A data transmission system comprising:

at least two of the data transmission stations of claim 7;

a clock bus interconnecting the clock terminals of the stations; and

means which maintain the clock bus at the second voltage level in the absence of forcing by the stations.

9. A system for data transmission comprising:

(A) at least two master transmitting stations which are capable of controlling data transmission, each comprising;

(a) a clock terminal;

(b) a data terminal;

(c) a time slot generator which produces a periodic clock signal at the clock terminal by first forcing the clock terminal to a first voltage level for a first interval of predetermined duration, by then allowing the clock terminal to assume a second voltage level for a clock pulse interval of predetermined duration, and by then again forcing the clock terminal to the first voltage level;

(d) means which detect the voltage level at the clock terminal and which cause the time slot generator to start the first interval whenever the voltage level at the clock terminal changes from the second voltage level to the first voltage level;

(e) means for producing a start signal which indicates that the master station is prepared to control data transmission allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;

(f) means for producing a stop signal which indicates that the master station is finished controlling data transmission by forcing the voltage level at the data terminal to the first voltage level during a first fraction of the clock pulse interval and by then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval;

(g) means for transmitting binary data by forcing the voltage at the data terminal to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage at the data terminal to assume the second voltage level during an entire clock pulse interval to transmit a second data value;

(B) at least one receiving station comprising a data terminal and a clock terminal;

(C) a data bus which interconnects the data terminals of all of the stations;

(D) a clock bus which interconnects the clock terminals of all of the stations; and

(E) means which maintain the buses at the second voltage level in the absence of forcing by the stations.

10. A system for data transmission comprising:

(A) at least two master transmitting stations which are capable of controlling data transmission, comprising each;

(a) a clock terminal;

(b) a data terminal;

(c) means for producing a clock signal at the clock terminal by allowing the clock terminal to assume a second voltage level for each of a series of periodic clock pulse intervals and by forcing the clock terminal to a first voltage level at all other times during production of the clock signal;

(d) means for producing a start signal which indicates that the master station is prepared to control data transmission by allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;

(e) means for producing a stop signal which indicates that the master station has finished controlling data transmission by forcing the voltage level at the data terminal to the first voltage level during a first fraction of a clock pulse interval and then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval; and

(f) means for transmitting binary data by forcing the voltage at the data terminal to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage at the data terminal to assume the second voltage level during an entire clock pulse interval to transmit a second data value;

(B) at least one receiving station comprising a data terminal and a clock terminal;

(C) a data bus which interconnects the data terminals of all of the stations;

(D) a clock bus which interconnects the clock terminals of all the stations; and

(E) means which maintain the buses at the second voltage level in the absence of forcing by the stations.

11. In a system for data transmission, the improvement comprising:

(A) a master transmitting station which is capable of controlling data transmission, comprising;

(a) a clock terminal;

(b) a time slot generator which produces a periodic clock signal at the clock terminal by first forcing the clock terminal to a first voltage level for a first interval of predetermined duration, by then allowing the clock terminal to assume a second voltage level for a second interval of predetermined duration, and by then again forcing the clock terminal to the first voltage level; and

(c) means which detect the voltage level at the clock terminal and which cause the time slot generator to start the first interval whenever the voltage level at the clock terminal changes from the second voltage level to the first voltage level;

(B) at least one receiving station comprising a clock terminal;

(C) a clock bus which interconnects the clock terminals of all of the stations; and

(D) means which maintain the clock bus at the second voltage level in the absence of forcing by the stations.

12. The system of claim 11 comprising at least two of said master transmitting stations.

13. A data tansmission station comprising:

(a) a clock terminal;

(b) a data terminal;

(c) means for producing a clock signal at the clock terminal by allowing the clock terminal to assume a second voltage level for each of a series of periodic clock pulse intervals and by forcing the clock terminal to a first voltage level at all other times during production of the clock signal;

(d) means for producing a start signal which indicates that the station is prepared to transmit data by allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;

(e) means for producing a stop signal which indicates that the station is finished transmitting data by forcing the voltage level at the data terminal to the first voltage level during a first fraction of a clock pulse interval and by then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval;

(f) means for transmitting binary data by forcing the voltage at the data terminal to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage at the data terminal to assume the second voltage level during an entire clock pulse interval to transmit a second data value; and

(g) means for establishing priority if a plurality of interconnected stations simultaneously attempt to control data transmission which detect the voltage level at the data terminal and which cause the station to allow both the clock terminal and the data terminal to assume the second voltage level for at least a predetermined interval after detection of the first voltage level on the data terminal during a clock interval in which the station has allowed the data terminal to assume the second voltage level.

14. The station of claim 13 wherein the means for producing the clock signal comprises:

a time slot generator which produces a periodic clock signal at the clock terminal by first forcing the clock terminal to a first voltage level for a first interval of predetermined duration, by then allowing the clock terminal to assume a second voltage level for a second interval of predetermined duration, and by then again forcing the clock terminal to the first voltage level, and

means which detect the voltage level at the clock terminal and which cause the time slot generator to start the first interval whenever the voltage level at the clock terminal changes from the second voltage level to the first voltage level.

15. A data transmission system comprising either at least two of the stations of claim 13 or at least two of the stations of claim 14;

a clock bus which interconnects the clock terminals of the stations; and

a data bus which interconnects the data terminals of the stations.

16. A method of data transmission on a data transmission system which comprises a plurality of stations, each station having a data terminal and a clock terminal, the data terminals of all stations being interconnected by a data bus and the clock terminals of all stations being interconnected by a clock bus, comprising:

transmitting a clock signal from a first master station along the clock bus by allowing the clock terminal of the first master station to assume a second voltage level during each of a series of periodic clock pulse intervals and by forcing the clock terminal of the first master station to a first voltage level at all other times during transmission of the clock signal;

transmitting a start signal, which indicates that the first master station is prepared to control data transmission, by allowing the data terminal of the first master station to assume a second voltage level during a first fraction of a clock pulse interval and then forcing the voltage level at the data terminal of the first master station to a first voltage level during said clock pulse interval;

transmitting a stop signal which indicates that the first master station has finished controlling data transmission by forcing the voltage level at the data terminal of the first master station to the first voltage level during a first fraction of the clock pulse interval and by then allowing the voltage level at the data terminal of the first master station to transition to the second voltage level during the same clock pulse interval; and

transmitting binary data by forcing the voltage level of a data terminal of a station to the first voltage level during an entire clock pulse interval to transmit a first data value and by allowing the voltage level at the data terminal of said station to assume the second voltage level during an entire clock pulse interval to transmit a second data value.

17. The method of claim 16 wherein the step of transmitting the clock signal comprises:

forcing the clock terminal of the first master station to a first voltage level for a first interval of predetermined duration, then allowing the clock terminal of the first master station to assume a second voltage level for a second interval of predetermined duration, and then again forcing the clock terminal to the first voltage level, and

detecting the voltage level at the clock terminal of the first master station and starting said first interval whenever the voltage level at the clock terminal changes from the second voltage level to the first voltage level,

and further comprising the step of creating a wired logic function on the clock bus by pulling the clock bus to the second voltage level in the absence of forcing by any of the stations.

18. The method of claim 16 or 17 wherein the system includes at least two master transmitting stations each of which is capable of transmitting a clock signal and further comrpising the step of:

preventing interference between simultaneously transmitting master stations by inhibiting the master stations from initiating transmission of a clock signal at such times that said master stations detect that a clock signal is already present on the clock bus.

19. A method of operating a data transmission system which includes a plurality of master transmitting stations each having a clock terminal, the clock terminals of all stations being interconnected by a bus, comprising the steps of:

creating a wired logic function on the bus by pulling the bus toward a second voltage level in the absence of forcing by any of the stations; and

synchronizing transmission of clock signals by simultaneously transmitting master stations by causing each master station to first force the clock terminal to a first voltage level for a first voltage interval having a duration which is locally predetermined for each master station, by then allowing the clock terminal of each master station to assume a second voltage level for a second interval having a duration which is locally predetermined for each master station, and by then causing each master station to again force the clock terminal to the first voltage level and by causing each master station to start said first interval whenever the voltage level on the clock bus changes from the second voltage level to the first voltage level.

20. The method of claim 19 further comprising the step of arbitrating priority if a plurality of interconnected master stations simultaneously attempt to control data transmission by pulling a data bus to a second voltage level in the absence of forcing by any master transmitting station, determining the voltage level on the data bus during data transmission, identifying master stations which have allowed the data bus to assume the second voltage level at times when the data bus is, in fact, at the first voltage level, and causing the identified master stations to cease data transmission for a period of time following such identification.

21. A communication system comprising:

a first plurality of transmitting and receiving stations including at least one master station and at least one slave station;

a data bus for transporting a series of data bits between at least one transmitting station and at least one receiving station;

a clock bus for transporting a synchronizing clock signal in synchronism with each data bit;

each bus further comprising logic means for forming a wired logic function between levels which denote a first and a second logic value respectively which are transmitted by the stations so that the level of the bus can be pulled to the first logic value by any station presenting a signal having the first logic value to the bus thereby masking any signal having the second logic value that may be presented to the bus;

each transmitting station comprising data transmitting means which, in each bit cell of a selected bit cell sequence, present a respective data bit on the data bus for a period of time which covers the duration of the associated clock pulse, including the edges thereof;

wherein each master station comprises;

(a) clock transmitting means which generate a series of clock pulses, each having the second logic value, on the clock bus to define a series of bits cells;

(b) means which form a first stop signal by forming a signal transition on the data bus from said first logic value to said second logic value, during the presence of a signal of the second logic value on the clock bus;

(c) means which form a first start signal by forming a signal transition on the data bus from said second logic value to said first logic value during the presence of a signal of the second logic value on the clock bus;

all non-master stations connected to the system comprising means for continuously presenting said second logic value to the clock bus and any non-transmitting station connected to the system comprising means for continuously presenting said second logic value to the data bus during said selected bit cell sequences.

23. A communication system as claimed in claim 21 wherein there may be a plurality of simultaneously transmitting master stations connected to the busses, wherein each of said master stations further comprise:

a time slot generator having an input for receiving a second start signal from the clock bus;

a detector for detecting a signal transition on the clock bus as a representation of said second start signal, which signal is produced by the combination of the first station which supplies a clock signal transition from said second to said first logic value and the last station which supplies a signal transition from said first to said second logic value, and for supplying an end signal after termination of a time slot which is started thereby;

said clock transmitting means in said master stations further forming a modified signal for the clock bus under the control of said end signal.

24. A communication system as claimed in claim 23 wherein said master stations further comprise detection means for detecting, during a clock pulse, a discrepancy between a logic value which is present on the data bus and logic value which is presented to the data bus by its own data transmitting means and

means for controlling a switch-over of said master station to a non-master condition upon the detection of such discrepancy.

25. A communication system as claimed in claim 21 wherein, in at least one master station, said data transmitting means and said means which form a first start signal further function to start a data transport operation by successively forming:

the first start signal, a first series of at least two data bits having the first logic value, a second series of at least one data bit having the second logic value, and a second start signal which corresponds to the first start signal.

26. A communication system as claimed in claim 25 wherein all stations connected to the system comprise interrogation means having a dead time which is shorter than the length of the first series of data bits.

27. A communication system as claimed in claim 26 further comprising a slave station having data transfer means for communicating data bits with the data bus in bit cells which are at least two times shorter than the dead time.

28. A communication system as claimed in claim 25 further comprising a slave station which includes means for resetting the slave station and for receiving an address on said data bus after reception of said second start signal.

29. Apparatus which operates as a master transmitter for data transmission comprising:

a data terminal for communicating a series of data bits;

a clock terminal for communicating a synchronizing clock signal, which defines a bit cell in synchronism with each data bit;

wherein the terminals have a low output impedance for a first logic value locally presented on said terminals and the terminals have a substantially higher output impedance for a second logic value locally presented on said terminals;

clock transmitting means which generate a clock pulse at the clock terminal which has the second logic value in each bit cell;

data transmitting means which generate a respective data bit on the data terminal for a period of time which covers the duration of the associated clock pulse, including the edges thereof, in each bit cell of selected bit cell sequences;

means which form a stop signal by forming a signal transition at the data terminal from said first to said second logic value during the generation of a signal of the second logic value at the clock terminal; and

means which form a first start signal by forming a signal transition at the data terminal from said second logic value to said first logic value during generation of a signal of the second logic value on the clock terminal.

30. Apparatus as claimed in claim 29, comprising a time slot generator having:

an input for receiving a second start signal from the clock terminal;

detector means which detect a signal transition at the clock terminal as an exclusive representation of said second start signal, which signal is produced by the combination of a clock signal transition from said second to said first logic value and by a clock signal transition from said first to said second logic value; and

means which supply an "end" signal after termination of a time slot which is started thereby;

and wherein said clock transmitting means further forms a modified clock signal under control of said "end" signal.

31. Apparatus as claimed in claim 30, further comprising means which detect a discrepancy between a logic value which is present at the data terminal and a data bit which is presently generated by the data transmitting means during a clock pulse and means for controlling a switch-over of the master station to a non-master station condition upon detection of such discrepancy.

32. Apparatus which operates as a master receiver for data transmission comprising:

a data terminal for communicating a series of data bits;

a clock terminal for communicating a synchronizing clock signal, which defines a bit cell in synchronism with each data bit;

wherein the terminals have a low output impedance for a first logic value locally presented on said terminals and the terminals have a substantially higher output impedance for the second logic value locally presented on said terminals;

clock transmitting means which generate a clock pulse having the second logic value in each bit cell at the clock terminal;

means for continuously generating a signal having said second logic value which is overridable by a lower impedance signal of said first logic value in each bit cell of selected bit cell sequences at the data terminal;

means which form a stop signal by forming a signal transition at the data terminal from said first to said second logic value during the generation of a signal of the second logic value on the clock terminal;

means which form a start signal by forming a signal transition at the data terminal from said second logic value to said first logic value during presentation of a signal of the second logic value on the clock terminal.

33. Apparatus which operates as a slave transmitter for data transmission comprising:

a data terminal for communicating a series of data bits;

a clock terminal for communicating for a synchronizing clock signal which defines a bit cell in synchronism with each data bit;

wherein the data terminal has a low output impedance for a first logic value locally presented on said data terminal and the data terminal has a substantially higher output impedance for a second logic value locally presented on said data terminal; and

data transmitting means which generate a respective data bit at the data terminal for a period of time which covers the duration of a second logic value clock pulse signal, including the edges thereof, which is received at the clock terminal in each bit cell of selected bit cell sequences.

34. Apparatus which operates as a slave receiver for data transmission comprising:

a data terminal for receiving a series of data bits;

a clock terminal for receiving a synchronizing clock signal which defines a bit cell in synchronism therewith for each data bit;

means which continuously generate a second logic value at the clock terminal which is overridable by a lower impedance signal of a first logic value, during each bit cell of selected bit cell sequences;

means which continuously generate said second logic value at the data terminal which is overridable by a lower impedance signal of said first logic value, in each bit cell of said bit cell sequences;

means which send an acknowledge bit which directly follows said bit cell sequence; and

means which selectively control a transition of said apparatus to a non-receiver condition in response to an eighth bit of an eight bit data sequence which is received at the data terminal.

35. An apparatus as claimed in claim 34, comprising 7-bit address comparator means which respond to earlier bits of a received data sequence.