Method of making active solid state devices

• US 4,690,714 A
• Filed: 01/31/1983
• Issued: 09/01/1987
• Est. Priority Date: 01/29/1979
• Status: Expired due to Term

• Current Assignee: LI Second Family Limited Partnership
• Original Assignee: Chou H. Li
• Inventors: Li, Chou H.
• Primary Examiner(s): Ozaki, George T.
• Application Number:
  US06/462,374
• Time in Patent Office: 1,674 Days
• Field of Search: 148/1.5, 148/33, 148/134, 148/171, 148/172, 148/173, 148/404, 29/569 L, 357/55
• US Class Current: 438/24
• CPC Class Codes: C30B 21/02 by normal casting or gradient freezing
• CPC Class Codes: C30B 21/04 by zone-melting
• CPC Class Codes: H01L 21/24 Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body H01L21/182 takes precedence
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 27/142 Energy conversion devices photovoltaic modules or arrays of single photovoltaic cells comprising bypass diodes integrated or directly associated with the devices H01L31/0443; photovoltaic modules composed of a plurality of thin film solar cells deposited on the same substrate H01L31/046
• CPC Class Codes: H01L 27/1446 in a repetitive configuration
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 31/00 Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof H10K30/00 takes precedence; devices consisting of a plurality of solid state components formed in, or on, a common substrate, other than combinations of radiation-sensitive components with one or more electric light sources, H01L27/00
• CPC Class Codes: H01L 31/06 characterised by potential barriers
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H01L 33/18 within the light emitting region
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy
• CPC Class Codes: Y10S 438/929 Eutectic semiconductor

Abstract

A method of making an integrated electrooptic solid state device array comprising forming a structure having a multiplicity of active, solid state electrooptic component bodies in a solid state device material, including arranging the component bodies in a geometrical pattern and forming the component bodies to a prespecified size of less than 15 microns each and to an accuracy to within a fraction of a micron, and providing at least one electronic rectifying barrier at each of the component bodies for the operation of each component body as an active solid state electrooptic component.

Claims

1. A method of making an integral, polycrystalline, active, solid-state device comprising the steps of:

non-eutectically forming a structure comprising a multiplicity of semiconductor material bodies separated from each other by other material, wherein each body comprises substantially single crystal material and there is physical, but not crystallographic, continuity between the single crystal bodies and the other material, said forming step further comprising forming electronic rectifying barriers within a fraction of a micron from a specified location at or adjacent at least a portion of the interface between each single crystal body and the adjacent other material, including selecting the characteristics of the semiconductor material and the other material to produce preselected electrical characteristics of said electronic rectifying barriers; and

providing electrical contacts to said structure for operation thereof as an active device.

2. A method as in claim 1 wherein the forming step includes preferentially diffusing hydrogen into said other material at a temperature below the melting point of the semiconductor material bodies to thereby improve selected electrical characteristics of said device.

3. A method of making an integrated, three-dimensional active solid-state device comprising the steps of:

forming a structure comprising a multiplicity of active, solid-state component bodies which are substantially the same in size and shape and are in a solid-state device material and are spaced thereby from each other, said forming step comprising arranging the component bodies in a specified three-dimensional geometrical pattern and forming the component bodies to a prespecified size of less than fifteen microns each and to an accuracy within a fraction of a micron; and

providing at least one electronic rectifying barrier within each of the component bodies for the operation of each component body as an active solid-state component.

4. A method as in claim 3 wherein said solid-state device material is selected from the group consisting of Si, Ge, GaAs, and GaP.

5. A method as in claim 3 wherein said forming step comprises forming the component bodies to within a fraction of a micron of a prespecified size.

6. A method of making an integrated electrooptic solid-state device array comprising the steps of:

forming a structure comprising a multiplicity of active, solid-state, electrooptic component bodies which are the same in shape and are in a solid-state device material which spaces them from each other, said forming step comprising arranging the component bodies in a selected geometric pattern and forming the component bodies to a prespecified size of less than fifteen microns each and to an accuracy of a fraction of a micron; and

providing at least one electronic rectifying barrier at each of the component bodies for the operation of each component body as an active, solid-state electrooptic component.

7. A method as in claim 6 in which said array generates heat when operating as an active state device array and in which said forming step comprises forming a structure in which the solid state device material is essentially a thermally conductive metal to help dissipate said heat.

8. A method as in claim 6 including sizing said component bodies so that at least a substantial portion thereof have sizes exceeding about 50 Angstroms.

9. A method as in claim 6 in which the forming step comprises forming a structure having two substantially parallel major surfaces, orienting the rectifying barriers generally transverse to said major surfaces, and extending the barriers along a major portion of the distance from one of the major surface to the other without allowing them to reach the other major surface.

10. A method as in claim 6 wherein said solid-state device material is selected from the group consisting of Si, Ge, GaAs, GaP, GaAlAs, and GaAlP.

11. A method as in claim 6 wherein said forming step comprising forming said component bodies to within a fraction of a micron of the prespecified size.

12. A method as in claim 6 wherein said forming step comprises adjusting the conditions of the formation step in terms of source material composition, growth temperature, and growth rate to control the dimensions of the component bodies to within a fraction of a micron.

13. A method as in claim 6 wherein said forming step comprises adjusting the conditions of the forming step to control the shape of the component bodies to within a fraction of a micron of a specified shape.

14. A method as in claim 6 wherein said forming step comprises adjusting the conditions of the forming step to control the spacing of the component bodies from each other to within a fraction of a micron of a specified spacing.

15. A method as in claim 6 including electronically isolating the component bodies from each other.

16. A method as in claim 6 wherein said forming step comprises forming the multiplicity of the component bodies to an array size of at least 50×

50.

17. A method as in claim 6 wherein said forming step comprises forming the multiplicity of the component bodies to an array size of at least 1000×

1000.

18. A method as in claim 6 wherein said providing step comprises providing the electronic rectifying barriers in the form of PN junction regions for the operation of the component bodies as electrooptic components so as to form an optoelectric array of the type selected from the group consisting of light-emitting array and light detecting array.

19. A method as in claim 18 wherein a front surface of each of the component bodies is surface contoured according to a prespecified shape.

20. A method as in claim 19 wherein each of said front surfaces is a paraboloidal surface of revolution contoured according to the following equation in the x-y plane:

space="preserve" listing-type="equation">Square root of (x·

x+y'"'"'·

y'"'"')-x=constant,

where the z-axis is the axis of revolution of the front surface of the component body and where y'"'"'=b+y for the portion of the curve above the x-axis, but y'"'"'=b-y for the portion below the x-axis, where 2b is the distance between two points in the x-y plane, the y-axis joins these two points, and the x-axis is normal to but bisects the straight line joining these two points.

21. A method as in claim 20 wherein said electrooptic device array is a light detector array and including providing a metallic reflecting surfaces on the paraboloidally contoured front surfaces of the detector component bodies.

22. A method as in claim 20 including providing and precisely positioning a light-collecting z-y plane exactly inside each PN junction region, which has respective collecting or terminating planes, so that the electron and hole of an electron-hole pair generated by an impacting radiation particle arrive at the respective collecting or terminating planes of the respective junction region at exactly the same time, thereby producing a fast, pure and strong output signal.

23. A method of improving the performance of a component which has a PN junction region and a radiation collecting plane in the region to receive radiation photons thereat and further has two terminal carrier collecting planes flanking the radiation collecting plane to respectively collect a hole and an electron generated by a radiation photon impacting at the radiation collecting plane, comprising directing a parallel beam of radiation photons at the component and paraboloidally focusing the beam onto a ring-shaped portion of the radiation collecting plane.

24. A method as in claim 23 in which the focusing step comprises reducing the ring-shaped portion of the plane to substantially zero thickness in the direction across the thickness of the PN junction region.

25. A method as in claim 23 including positioning the light collecting plane of the component relative to the terminal planes to ensure that the photon-generated hole and electron pair from each photon impacting at the light collecting plane arrive at the respective terminal collecting planes at exactly the same time.