Semiconductor device and a method of producing the same

• US 4,691,225 A
• Filed: 01/28/1983
• Issued: 09/01/1987
• Est. Priority Date: 02/05/1982
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Murakami, Gen, Gappa, Takeshi
• Primary Examiner(s): Sikes, William L.
• Assistant Examiner(s): Gonzalez, Frank
• Application Number:
  US06/462,060
• Time in Patent Office: 1,677 Days
• Field of Search: 174/52 FP, 174/52 PE, 174/68.5, 361/386, 361/401, 357/73, 357/74, 357/80, 357/81
• US Class Current: 257/693
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H05K 3/0097 : Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards H05K3/0052 takes precedence
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence

Abstract

A semiconductor device comprising a package base whose material is glass epoxy or the like, a plurality of leads which are formed in a manner to extend from the front surface to the rear surface of the package base, a semiconductor element which is fastened to the package base and which is electrically connected to the leads, and a resin which seals, at least, the semiconductor element and electrical connection parts between the element and the leads.

Claims

1. A semiconductor device comprising:

a base having a front surface, rear surface and side surface, said side surface extending between the front surface and the rear surface, said side surface being nonplanar and having portions which are indented into the base, said front surface being formed in the shape of a square, and said base being made of a material selected from the group consisting of glass epoxy, glass phenol, tirazine, paper phenol, polyimide sand polyester;

a semiconductor element fastened on said front surface;

a plurality of inner leads formed on said front surface so as to surround said semiconductor element;

a plurality of outer leads formed on said rear surface;

a plurality of connective portions connecting said plurality of inner leads respectively to said plurality of outer leads, said plurality of connective portions being formed on the indented portions of said side surface of said base;

a plurality of electrical connection parts connecting between said semiconductor element and said plurality of inner leads; and

a resin sealing, at least, said semiconductor element and said plurality of electrical connection parts.

2. A semiconductor device as defined in claim 1, further comprising a protective resin covering the inner leads in such a manner that the ends thereof to which the electrical connection parts are attached are left exposed.

3. A semiconductor device as defined in claim 1, wherein said semiconductor element is fastened in a recess which is formed in the front surface of said base.

4. A semiconductor device as defined in claim 3, wherein a heat sink is formed on the rear surface of said base.

5. A semiconductor device as defined in claim 4, wherein said heat sink is formed on the rear surface opposite to said recess.

6. A semiconductor device as defined in claim 1, wherein said plurality of electrical connection parts are wires.

7. A semiconductor device as defined in claim 6, wherein the parts of said inner leads contacted by said wires are coated with a coating of gold.

8. A semiconductor device as defined in claim 1, wherein said base is in the form of a plate.

10. A semiconductor device as defined in claim 1, wherein said plurality of connective portions are formed by depositing an electrically conductive material on said side surface to electrically connect one of said plurality of inner leads with a respective one of said plurality of outer leads.

11. A multiple frame as defined in claim 10, having a position, surrounded by said inner leads, on each base region for situating a semiconductor element on each base region.

12. A multiple frame as defined in claim 11, wherein said position is a recess formed in the substrate.

13. A semiconductor device as defined in claim 1, wherein said plurality of inner leads, said plurality of outer leads and said pluraity of connective portions are not integrally formed.

14. A semiconductor device as defined in claim 1, wherein said base is adapted to be connected to a printed circuit board, and wherein said base has substantially the same coefficient of thermal expansion as that of the printed circuit board.

15. A semiconductor device as defined in claim 1, further comprising a printed circuit board, the base being connected to the printed circuit board, the printed circuit board being comprised of conductive patterns formed on a substrate, and wherein the coefficient of thermal expansion of the base is substantially the same as that of the printed circuit board.

16. A semiconductor device as defined in claim 15, wherein the material of the base is the same as that of the substrate of the printed circuit board.

17. A semiconductor device as defined in claim 15, wherein the base is connected to the printed circuit board by directly connecting said outer leads to corresponding portions of the conductive patterns.

18. A semiconductor device as defined in claim 1, wherein the indented portions extend form the front surface to the rear surface of the base.

19. A semiconductor device comprising:

a base having a front surface, rear surface and side surface, said side surface extending between the front surface and the rear surface, said side surface being nonplanar and having portions which are indented into the base, said front surface being formed in the shape of square, and said base being made of a material selected from the group consisting of glass epoxy, glass phenol, triazine, paper phenol, polyimide and polyester;

a hole penetrating through the base between said front surface and rear surface;

a heat sink formed on said rear surface so as to close said hole;

a plurality of inner leads formed on said front surface so as to surround said hole;

a plurality of outer leads formed at said rear surface;

a plurality of connective portions connecting said plurality of inner leasds respectively to said plurality of outer leads, said plurality of connective portions being formed on the indented portions of said side surface of the base;

a semiconductor element fastened on said heat sink in the hole;

a plurality of electrical connection parts connecting between said semiconductor element and said plurality of inner leads; and

a resin sealing, at least, said semiconductor element and said plurality of electrical connection parts.

9. A semiconductor device as defined in claim 24, wherein said base is formed of glass fibers filled with an epoxy resin.

20. A semiconductor device as defined in claim 19, wherein said plurality of electrical connection parts are wires.

21. A semiconductor device as defined in claim 19, wherein said pluraity of outer leads are formed so as to surround said heat sink.

22. A semiconductor device as defined in claim 19, wherein said base is in the form of a plate

23. A semiconductor device as defined in claim 19, wherein said plurality of connective portions are formed by depositing an electrically conductive material on said side surface to electrically connect one of said plurality of inner leads with a respective one of said plurality of outer leads.

24. A semiconductor device as defined in claim 19, wherein said plurality of inner leads, said plurality of outer leads and said plurality of connective portions are not integrally formed.

25. A semiconductor device as defined in claim 19, wherein said base is adapted to be connected to a printed circuit board, and wherein said base has substantially the same coefficient of thermal expansion as that of the printed circuit board.

26. A semiconductor device as defined in claim 19, further comprising a printed circuit board, the base being connected to the printed circuit board, the printed circuit board being comprised of conductive patterns formed on a substrate, and wherein the coefficient of thermal expansion of the base is substantially the same as that of the printed circuit board.

27. A semiconductor device as defined in claim 26, wherein the material of the base is the same as that of the substrate of the printed circuit board.

28. A semiconductor device as defined in claim 26, wherein the base is connected to the printed circuit board by directly connecting said outer leads to corresponding portions of the conductive patterns.

29. A semiconductor device as defined in claim 19 wherein the indented portions extend from the front surface to the rear surface of the base.

30. A multiple frame comprising:

an oblong substrate having a prescribed thickness and adapted to be separated into plural base regions, said oblong substrate being made of a material selected from the group consisting of glass epoxy, glass phenol, triazine, paper phenol, polyimide and polyester;

a plurality of slots extending through said substrate so as to determine respective base regions;

a plurality of inner leads formed on a surface of said respective base regions;

a plurality of outer leads formed at an opposite surface, of said respective base regions, to said surface of the respective base regions on which the plurality of inner leads are formed;

a plurality of connective portions connecting said plurality of inner leads respectively to said plurality of outer leads, said plurality of connective portions being formed on side surfaces of said plural base regions determined by said plurality of slots.

31. A multiple frame as defined in claim 30, wherein said side surfaces of said plural base regions are nonplanar and have portions which are indented into the base regions, and wherein said plurality of connective portions are formed on the indented portions of said side surfaces of said plural base regions.

32. A multiple frame as defined in claim 31, wherein indented portions extend from said surface to said opposite surface of said plural base regions

33. A multiple frame as defined in claim 30, wherein said side surfaces of the plural base regions are determined by said plurality of slots.