Current fed inverter

• US 4,691,275 A
• Filed: 06/04/1986
• Issued: 09/01/1987
• Est. Priority Date: 06/04/1986
• Status: Expired due to Fees

• Current Assignee: SMI Electronics Corporation
• Original Assignee: Superior Manufacturing & Instrument Corp.
• Inventors: Moscovici, Poldi
• Primary Examiner(s): Wong, Peter S.
• Application Number:
  US06/870,377
• Time in Patent Office: 454 Days
• Field of Search: 363/17, 363/22-26, 363/97-98, 363/143, 323/346
• US Class Current: 363/143
• CPC Class Codes: H02M 3/3378 in a push-pull configuration of the parallel type H02M3/3374 takes precedence

Abstract

A current fed inverter circuit is provided in which there are two interconnected circuits, each of which shares a common inductor and transformer primary. These interconnected circuits are arranged so that an operator selector switch can connect the two circuits in a first configuration to form a current fed half bridge circuit and in a second, different configuration, to form a current fed push-pull circuit.

Claims

1. A current fed inverter circuit for accommodating two different input voltages from an input source of direct current or rectified alternating current, which comprises:

a first circuit having an inductor and a transformer primary winding;

a second circuit having said inductor and said transformer primary winding;

an output circuit including a transformer secondary winding magnetically coupled to said transformer primary winding;

means for alternately modifying current flow in the first circuit and the second circuit; and

operator selector means for connecting said first and second circuits in a first configuration to form a current fed half bridge circuit to accommodate the higher of the two input voltages and in a second, different configuration, to form a current fed push-pull circuit to accommodate the lower of the two input voltages.

2. A current fed inverter circuit as described in claim 1, in which said output circuit further includes means for rectifying the output of said secondary winding, output terminals, and a boost circuit including said inductor connected across the output terminals.

3. A current fed inverter circuit as described in claim 2, said output circuit further including a rectifier in series with said inductor;

and a filter capacitor connected across the output terminals and in parallel with said boost circuit.

4. A current fed inverter circuit as described in claim 1, said modifying means comprising first switching means for opening and closing said first circuit;

second switching means for opening and closing said second circuit; and

means for alternately controlling said first and second switching means.

5. A current fed inverter circuit as described in claim 4, said controlling means comprising means for closing said first switching means when said second switching means is open and for opening said first switching means when said second switching means is closed.

6. A current fed inverter circuit as described in claim 5, said first and second switching means comprising first and second transistors, and said controlling means being coupled to the control electrodes of said transistors to place each transistor in an opposite state of conduction from the other transistor.

7. A current fed inverter circuit as described in claim 1, said input source having a positive terminal and a negative terminal;

said first circuit including a first point and a second point with a capacitor in series between said first and second points;

said second circuit including a third point and a fourth point with a capacitor in series between said third and fourth points;

means connecting said positive terminal to said first point;

means connecting said negative terminal to said fourth point;

said operator selector means including switching means for connecting said second point to said third point to form the half bridge configuration, and for disconnecting said second point from said third point and connecting said positive terminal to said third point and said negative terminal to said second point to form the push-pull configuration.

8. A current fed inverter circuit for accommodating two different input voltages from an input source of direct current or rectified alternating current to provide a positive terminal and a negative terminal, which comprises:

a first circuit having a first inductor and a first transformer primary winding;

a second circuit having a second inductor and a second transformer primary winding;

an output circuit including a first transformer secondary winding magnetically coupled to said first transformer primary winding and a second transformer secondary winding magnetically coupled to said second transformer primary winding;

means for alternately modifying the current flow in the first circuit and the second circuit;

means for connecting said positive terminal to said first circuit and said negative terminal to said second circuit;

operator selector means for connecting said first and second circuits in a first configuration to form a current fed half bridge circuit to accommodate the higher of the two input voltages and in a second, different configuration to form a current fed push-pull circuit to accommodate the lower of the two input voltages.

9. A current fed inverter circuit as described in claim 8, said first and second inductors comprising portions of a common inductor device and said first and second transformer primary windings comprising primary windings of a single transformer.

10. A current fed inverter circuit as described in claim 8, said first and second transformer primary windings comprising primary windings of a single transformer and said first and second transformer secondary windings comprising secondary windings of said single transformer.

11. A current fed inverter circuit as described in claim 10, said output circuit further including means for rectifying the output of the secondary windings, output terminals, and a boost circuit including a third inductor and series rectifier connected across the output terminals.

12. A current fed inverter circuit as described in claim 8, said first and second inductors comprising portions of a common inductor device.

13. A current fed inverter circuit as described in claim 8, said modifying means comprising first switching means for opening and closing said first circuit;

second switching means for opening and closing said second circuit; and

means for alternatively controlling said first and second switching means.

14. A current fed inverter circuit as described in claim 13, said controlling means comprising means for closing said first switching means when said second switching means is open and for opening said first switching means when said second switching means is closed.

15. A current fed inverter circuit as described in claim 14, said first and second switching means comprising first and second transistors, and said controlling means being coupled to the control electrodes of said transistors to place each of said transistors in an opposite state of conduction from the other transistor.

16. A current fed inverter circuit as described in claim 8, said first circuit including a first point and a second point with a capacitor in series between said first and second points;

said second circuit including a third point and a fourth point with a capacitor in series between said third and fourth points;

said positive terminal being connected to said first point and said negative terminal being connected to said fourth point;

said operator selector means including switching means for connecting said second point to said third point to form the half bridge configuration, and for disconnecting said second point from said third point and for connecting said positive terminal to said third point and said negative terminal to said second point to form the push-pull configuration.

17. A current fed inverter circuit for accommodating two different input voltages from an input source of direct current or rectified alternating current to provide a positive terminal and a negative terminal, comprising:

a first circuit having a first inductor and a first transformer primary winding;

a second circuit having a second inductor and a second transformer primary winding;

an output circuit including a first transformer secondary winding magnetically coupled to said first transformer primary winding and a second transformer secondary winding magnetically coupled to said second transformer primary winding;

said first and second inductors comprising portions of a common inductor device;

said first and second transformer primary windings comprising primary windings of a single transformer;

said first and second transformer secondary windings comprising secondary windings of said single transformer;

said output circuit further including means for rectifying the output of the secondary windings, output terminals, and a boost circuit including a third inductor and a series rectifier connected across the output terminals;

means for connecting said positive terminal to said first circuit and said negative terminal to said second circuit;

means for alternately modifying the current flow in the first circuit and the second circuit, said modifying means comprising first switching means for opening and closing said first circuit, second switching means for opening and closing said second circuit, and means for alternatively controlling said first and second switching means;

said controlling means comprising means for closing said first switching means when said second switching means is open and for opening said first switching means when said second switching means is closed;

said first and second switching means comprising first and second transistors, and said controlling means being coupled to the control electrodes of said transistors to place each transistor in an opposite state of conduction from the other transistor;

means for connecting said positive terminal to said first circuit and said negative terminal to said second circuit;

operator selector means for connecting said first and second circuits in a first configuration to form a current fed half bridge circuit to accommodate the higher of the two input voltages and in a second, different configuration, to form a current fed push-pull circuit to accommodate the lower of the two input voltages.

18. A current fed inverter circuit as described in claim 17, said first circuit including a first point and a second point with a capacitor in series between said first and second points;

said second circuit including a third point and a fourth point with a capacitor in series between said third and fourth points;

said positive terminal being connected to said first point and said negative terminal being connected to said fourth point;

said operator selector means including switching means for connecting said second point to said third point to form the half bridge configuration, and for disconnecting said second point from said third point and for connecting said positive terminal to said third point and said negative terminal to said second point to form the push-pull configuration.