Data processing system simultaneously carrying out address translation of a plurality of logical addresses

• US 4,691,281 A
• Filed: 04/13/1984
• Issued: 09/01/1987
• Est. Priority Date: 04/13/1983
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Furui, Toshiyuki
• Primary Examiner(s): Williams, Jr., Archie E.
• Assistant Examiner(s): Clark, David L.
• Application Number:
  US06/599,869
• Time in Patent Office: 1,236 Days
• Field of Search: 364/200, 364/200 MS File, 364/900 MS File
• US Class Current: 711/207
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Abstract

In a data processing system for use in carrying out address translation of a preselected logical address so as to access a sequence of data elements stored in a memory (32) with an interval left between two adjacent ones of the data elements, a request control circuit (40) decides an element number in each cycle with reference to a logical distance (D) determined by the interval. The memory can be accessed in each cycle by a plurality of real addresses which are equal in number to the element number and which are calculated from the logical distance and the preselected logical address. Preferably, an address translation unit (80) is supplied with the preselected logical address and a part of the logical distance to produce a plurality of consecutive real page addresses (RPE and RPO) one of which corresponds to the preselected logical address. An address generator (50) produces a predetermined number of local logical addresses (EA₀ ˜EA₃) in response to the logical distance and the preselected logical address. The local logical addresses are combined with the consecutive real page addresses in an address combination circuit (100 ) to form local real addresses equal in number to the predetermined number. The local real addresses are restricted in number to the element number by a memory access controller (135) to be supplied to the memory as the real addresses.

Claims

1. A data processing system for use in accessing in each cycle a memory which has a plurality of real addresses located in a real address space and which stores a plurality of sequence of data elements, the data elements of each sequence being stored in the real addresses equidistantly spaced apart from one another in said real address space by a real distance which is representative of an address distance between two adjacent ones of the real addresses for each sequence and which is predetermined for each sequence, said data processing system comprising:

logical address specifying means (36) for identifying a preselected one of logical addresses of a logical address space in each cycle that corresponds to a preselected one of the data elements of each sequence;

a distance specifying means (37) for identifying the logical distance that corresponds to the real distance between data elements of each sequence in each cycle;

deciding means (40) coupled to said distance specifying means and responsive to said logical distance for determining an element number which is the number of data elements to be simultaneously read out for each sequence;

address calculating means (50, 80, 100,

     135) coupled to said deciding means, said distance specifying means and said logical address specifying means, and responsive to said preselected logical address, said logical distance, and said element number for calculating the specific addresses of a number of data elements which together equal in number said element number and are spaced apart from one another by the real distance which corresponds to said logical distance and which include a preselected real address for storing said preselected one of the data elements as a leading data element; and

means coupled to said address calculating means and responsive to said specific addresses for accessing said memory to produce those of the data elements of each sequence in each cycle including said preselected one of the data elements which in the aggregate equal in number said element number.

2. A data processing system as claimed in claim 1, said memory comprising a plurality of consecutively numbered real pages with each real page subdivided into a plurality of memory locations, each of said real addresses consisting of a real page address and a real internal address, the real page addresses identifying the respective real pages, the real internal addresses identifying the respective memory locations of each real page, said logical address space comprising a plurality of logical pages with each logical page subdivided into logical positions equal in number to the memory locations of each real page, each of said logical addresses consisting of a logical page address and a logical internal address, the logical page addresses specifying the respective logical pages, the logical internal addresses specifying the respective logical positions of each logical page, said preselected logical address consisting of a preselected logical page address and a preselected logical internal address, wherein said address calculating means comprises:

address translation means for translating said preselected logical page address into translated real page addresses which are used in accessing those at least two of said real pages, one of said at least two real pages being accessible by said preselected real page address, the remaining at least one of said at least two real pages having the real page address numbered consecutive to said one of said at least two real pages;

address generating means responsive to said preselected logical page address and said preselected logical internal addresses and said logical distance for generating a predetermined number of local logical addresses one of which is identical with at least a part of a combination of said preselected logical page address and said preselected logical internal address and remaining ones of which are spaced apart by integral multiples of said logical distance from the logical position specified by said preselected logical page and said preselected logical internal addresses;

address combining means for combining said translated real page addresses with said local logical addresses to produce local real addresses which are equal in number to said predetermined number and which correspond to said local logical addresses, respectively; and

selecting means responsive to said local real addresses and said element number for selecting said specific addresses from said local real addresses.

3. A data processing system as claimed in claim 2, wherein said address generating means comprises:

supplying means responsive to said preselected logical page address and said preselected logical internal address for supplying at least a part of said preselected logical address to said combining means as said one local logical address;

calculation means responsive to said logical distance for calculating integral multiples of said logical distance which are equal in number to said predetermined number less one; and

summing means for summing said integral multiples and said at least a part of the preselected logical address to supply the remaining local logical addresses to said combining means.

4. A data processing system as claimed in claim 2, said logical pages being equal in number to two in the X-th power, each logical page address being of X bits where X is an integer, said X bits being divisible into a higher significant part of M bits and a lower significant parts of N bits, said logical pages being divided into logical page blocks which are equal in number to two to the N-th power and each of which consists of the logical pages equal in number to two to the M-th power, the higher significant part of said each logical address being further divided into a first part and a second part following the first part wherein said address translation means comprises:

translation buffers, two to the N-th power in number, which correspond to the respective logical page blocks for carrying out address translation for each of said logical page blocks, each of said translation buffers storing the first parts of the logical page addresses for each logical page block together with said translated real page addresses for the respective logical page addresses; and

buffer accessing means coupled to said logical address specifying means for accessing the respective translation buffers by using said second part of said preselected logical page address to make said translation buffers produce the translated real page addresses corresponding to said preselected logical page address.

5. A data processing system as claimed in claim 3, the preselected logical address being stored at a leading logical address in a current one of the cycles in said logical address specifying means, wherein said calculation means further calculates a product of said logical distance and said predetermined number;

said address generating means further comprises;

additional means coupled to said calculation means and said logical address specifying means for adding said product to said leading logical address in said current cycle to produce a result of addition; and

means for supplying said result of addition to said logical address specifying means as the preselected logical address used in a cycle following said current cycle.