Vertical interval data blanker

• US 4,691,354 A
• Filed: 04/10/1986
• Issued: 09/01/1987
• Est. Priority Date: 07/28/1983
• Status: Expired due to Fees

• Current Assignee: Zenith Electronics Corporation (LG Corporation)
• Original Assignee: Zenith Electronics Corporation (LG Corporation)
• Inventors: Palminteri, Craig R.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Koltak, Melissa L.
• Application Number:
  US06/850,208
• Time in Patent Office: 509 Days
• Field of Search: 358/114, 358/120, 358/122, 358/123, 358/124, 358/155, 358/148
• US Class Current: 380/226
• CPC Class Codes: H04N 7/1675 Providing digital key or authorisation information for generation or regeneration of the scrambling sequence pseudo-random number generators in general G06F7/58

Abstract

A stretched vertical interval pulse is developed by a transistorized integrating circuit supplied with a composite sync signal applied to a data recovery and unscrambler circuit in a television decoder. The decoder includes a pair of transmission gates that are controlled respectively by VNX and VIX signals developed in the unscrambler circuit. The VNX signal is supplied through an OR gate to the normal transmission gate and the output of the vertical interval pulse stretcher is applied to the other input of the OR gate for delaying cutoff of the transmission gate by the VNX signal until occurrence of horizontal line 10, thus precluding blanking of post equalizing pulses.

Claims

1. In an addressable cable television signal decoder of the type including means for recovering data carried on one or more horizontal lines occurring during the vertical blanking interval of a conventional television signal that includes a serrated vertical sync pulse and pre and post equalizing pulses, and including data receiver and unscrambler means for recovering said data, developing a VNX signal for blanking said data from said television signal and for generating a control signal by integration of said serrated vertical sync pulse to control generation of said VN signal, and a transmission gate controlled by said VNX signal;

the improvement comprising;

means for generating an additional stretched pulse signal by integration of said serrated vertical sync pulse;

gate means coupled to said transmission gate; and

means for applying said stretched pulse signal and said VNX signal to said gate means to delay blanking of said data by said VNX signal until after occurrence of said post equalizing pulses.

2. A decoder as set forth in claim 1 wherein the trailing edge of said stretched pulse signal occurs at horizontal line 10 in said vertical interval.

3. A decoder as set forth in claim 2 wherein said means for generating said stretched pulse signal include a transistor.

4. A decoder as set forth in claim 3 further including;

an R-C integrating network coupled to the input of said transistor;

means supplying said serrated vertical sync pulse to said integrating circuit; and

means coupling the output of said transistor to said gate means for supplying said stretched pulse signal thereto, said transistor being normally conductive until said serrated vertical sync pulse charges said integrating network.

5. A decoder as set forth in claim 4 wherein said gate means comprises an OR gate.

6. An addressable cable television signal decoder comprising:

means for receiving and detecting a television signal including a serrated vertical pulse and post equalizing pulses;

means for recovering data on one or more horizontal lines in the vertical blanking interval of said television signal;

means for remodulating said detected television signal to VHF channel 3/4;

means for developing a blanking signal for blanking said data from said remodulated television signal;

integrating means for developing a stretched vertical interval pulse from said serrated vertical pulse;

gate means for controlling blanking of said data from said remodulated television signal; and

means for applying said blanking signal and said stretched pulse to said gate means for delaying operation of said gate means by said blanking signal until after occurance of said post equalizing pulses.

7. A decoder as set forth in claim 6 wherein said integrating means includes a transistor and wherein said gate means comprises an OR gate.