Electro-mechanical integrator

• US 4,692,933 A
• Filed: 03/24/1986
• Issued: 09/08/1987
• Est. Priority Date: 03/24/1986
• Status: Expired due to Fees

• Current Assignee: Elsag International BV (ABB Limited)
• Original Assignee: Babcock & Wilcox Company (Babcock International Group PLC)
• Inventors: Wroblewski, David J., Robertson, John W. Jr.
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US06/843,369
• Time in Patent Office: 533 Days
• Field of Search: 377/39, 377/28, 377/29, 377/44, 377/55, 377/111, 377/114, 328/127, 371/30, 371/27, 73/1 R, 73/52, 73/112, 307/515
• US Class Current: 377/29
• CPC Class Codes: G01F 15/0755 involving digital counting
• CPC Class Codes: G01R 19/252 using analogue/digital converters of the type with conversion of voltage or current into frequency and measuring of this frequency
• CPC Class Codes: G06F 7/62 Performing operations exclusively by counting total number of pulses ; Multiplication, division or derived operations using combined denominational and incremental processing by counters, i.e. without column shift G06F7/68 takes precedence
• CPC Class Codes: G06F 7/68 using pulse rate multipliers or dividers pulse rate multipliers or dividers per seG06F7/70 takes precedence ; frequency division in electronic watches G04G3/02; frequency multiplication or division in oscillators H03B19/00; frequency dividing counters per se H03K23/00 - H03K29/00

Abstract

An electronic integrator for integrating a linear voltage signal utilizes a voltage-to-frequency converter for converting the voltage to input frequency. A binary counter counts pulses of the input frequency. The binary counter generates a first operating frequency which is applied to a scaling circuit and another calibration frequency which has a much higher rate than the operating frequency. Both, however are proportional to the input frequency. The scaling circuit scales the operating frequency to a selected extent to form a counting signal. Using the double pole switch, either the calibration frequency or the counting frequency are applied to a pulse counter which is either used to integrate the input voltage signal by counting up pulses of the scaled counting signal, or the integrator can be calibrated using the calibration frequency which quickly increments the pulse counter.

Claims

1. An electronic integrator for integrating a linear voltage signal over time, comprising:

input means for applying the linear voltage signal;

voltage-to-frequency conversion means for converting the linear voltage signal to an input frequency signal having a frequency proportional to the linear voltage signal;

a binary counter connected to said converter for counting pulses of the input frequency signal and for generating an operating frequency signal having a relatively low frequency, and a calibrating frequency signal having a relatively high frequency with respect to the operating frequency signal;

binary rate multiplying means connected to said binary counter for receiving the operating frequency and for generating a counting rate signal which has pulses that are at a scaled proportion of the operating frequency signal, said binary rate multiplying means having scaling means for changing the proportion;

a pulse counter for counting pulses of the counting rate signal and for counting pulses of the calibrating frequency signal; and

switch means having a first input connected to said binary counter for receiving the calibrating frequency signal, a second input connected to said binary rate multiplying means for receiving the counting rate signal, and an output connected to said pulse counter, said switch means being selectively switchable between a calibration position connecting said first input to said pulse counter for incrementing the pulse counter rapidly, and an operating position connecting said second input to said pulse counter for incrementing said pulse counter more slowly and at a rate proportional to the linear voltage signal.

2. An integrator according to claim 1, wherein said pulse counter has a numeric display for displaying the count of the pulse counter, said numeric display changing more rapidly when said switch means is in its calibration position than when said switch means is in its operating position.

3. An integrator according to claim 2, wherein said switch means comprises a double throw switch having a neutral off position where neither of said first and second inputs are connected to said output.

4. An integrator according to claim 3, wherein said double throw switch comprises a double pole double throw switch having additional inputs and an additional output, a power supply connected to said additional inputs, said additional output being connected to said pulse counter for powering said pulse counter, said switch in its off position supplying no power to said pulse counter.

5. An integrator according to claim 4, wherein said binary rate multiplying means comprises a plurality of binary rate multipliers connected in series, a first one of said multipliers in said series being connected to said binary counter for receiving the operating frequency signal and a last one of said multipliers in said series having an output, and an additional binary counter connected between said output of said last multiplier and said second input of said switch means.

6. An integrator according to claim 5, wherein said pulse counter includes amplifying means connected to said output of said switch means for amplifying the counting rate signal and the calibrating frequency signal, said amplifying means having a power input connected to said additional output of said double pole double throw switch.

7. An integrator acording to claim 1, wherein said switch means comprises a double throw switch having a neutral off position where neither of said first and second inputs are connected to said output.

8. An integrator according to claim 1, wherein said binary rate multiplying means comprises a plurality of binary rate multipliers connected in series, a first one of said multipliers in said series being connected to said binary counter for receiving the operating frequency signal and a last one of said multipliers in said series having an output, and an additional binary counter connected between said output of said last multiplier and said second input of said switch means.