Synchronized network system

• US 4,694,294 A
• Filed: 07/10/1985
• Issued: 09/15/1987
• Est. Priority Date: 07/12/1984
• Status: Expired due to Fees

• Current Assignee: Nissan Motor Co., Ltd.
• Original Assignee: Nissan Motor Co., Ltd.
• Inventors: Suzuki, Tadashi, Futami, Toru, Sakagami, Atsushi
• Primary Examiner(s): YUSKO, DONALD
• Application Number:
  US06/753,595
• Time in Patent Office: 797 Days
• Field of Search: 340/825.06, 340/825.5, 340/825.2, 340/825.21, 340/825.14, 340/825.07, 340/825.08, 370/82, 370/83, 370/95, 370/91, 370/92, 375/113, 375/117
• US Class Current: 709/248
• CPC Class Codes: G08C 15/12 the signals being represented by pulse characteristics in transmission link
• CPC Class Codes: H04L 12/40 Bus networks
• CPC Class Codes: H04L 12/43 with synchronous transmission, e.g. time division multiplex [TDM], slotted rings

Abstract

A network system including a data transmission line through which a serial data is transmitted, a synchronous signal line through which a synchronous signal transmission for controlling a transfer of the serial data is transmitted, and a plurality of data stations connected to both the signal transmission line and synchronous signal transmission line, each one of the data stations transferring the serial data to any of the other data stations in accordance with the synchronous signal, wherein a period over which the serial data is transmitted to the data signal transmission line is varied according to a length of the serial data.

Claims

1. A network system including a data transmission line through which a serial data is transmitted, a synchronous signals transmission line through which a synchronous signal for controlling a transfer of the serial data is transmitted, and a plurality of data stations connected to both data transmission line and synchronous signal transmission line, each one of the data stations transferring the serial data to any of the other data stations in accordance with the synchronous signal, comprising:

(a) first means for generating and outputting the synchronous signal to the synchronous signal transmission line, the synchronous signals having information bits of a constant period for selecting any of the data stations between which the serial data is transferred via the data transmission line and with which the transfer of the serial data is synchronized;

(b) second means for cyclically generating said information bits of the synchronous signal;

(c) third means for operatively inhibiting the transmission of said information bits to the synchronous signal transmission line; and

(d) fourth means responsive to the selection of any of the stations to transmit the serial data to the data transmission line by means of said information bits for actuating said third means to inhibit the transmission of said information bits to the synchronous signal transmission line over a period which is varied according to a length of the serial data transmitted to the data transmission line.

2. The network system according to claim 1, wherein said fourth means sends a first signal which indicates that the serial data is being transmitted to the other designated station from the selected data station via the data transmission line to said third means until completion of the transmission of the serial data.

3. The network system according to claim 2, wherein said third means comprises an AND gate and a clock pulse generator, one input terminal of said AND gate receiving a clock pulse signal having a predetermined period from said clock pulse generator and the other input terminal thereof receiving the first signal from said fourth means, for passing the clock pulse signal therethrough to said second means when the first signal is not received.

4. The network system according to claim 3, wherein said second means comprises:

(a) a shift register having a predetermined number of stages which shifts a logic signal of a previous stage thereof in synchronization with the clock pulse signal from said clock pulse generator via said AND gate;

(b) a logic element connected to said shift register for generating an M-series code having a period expressed as T_CM =tc×

(2ⁿ -1) together with said shift register, wherein tc denotes the predetermined period of the clock pulse and n denotes the predetermined number of stages of said shift register.

5. The network system according to claim 4, wherein the predetermined number of stages of said shift register is three and said logic element comprises an Exclusive OR gate, one input terminal thereof being connected to an output terminal of a third stage of said shift register, the other input terminal thereof being connected to an output terminal of a second stage of said shift register, and output terminal thereof being connected to an input terminal of a first stage of said shift register, so that a third order M-series code signal is generated.

6. The network system according to claim 4, wherein said first means comprises a modulator connected to the synchronous signal transmission line which modulates the M-series code signal generated by said shift register and logic element in synchronization with the clock pulse signal sent from the clock pulse generator via said AND gate so that the synchronous signal having said information bits of the constant period corresponding to the period of the M-series code is sent to the synchronous signal transmission line.

7. The network system according to claim 3, wherein fourth means comprises:

(a) fifth means for counting and storing the number of bits constituting the serial data to be transmitted to the data transmission line; and

(b) sixth means for holding the stored number of bits in said fifth means when the synchronous signal from said first means selects the data station having said fourth means to which the serial data is transmitted, counting decrementally the stored number of bits in synchronization with a timing at which each bit constituting the serial data is transmitted to the data transmission line, and outputting the first signal to said AND gate until the decremental count thereof result gives zero.

8. The network system according to claim 7, wherein a period from the timing at which one bit constituting the serial data is transmitted to the timing at which the subsequent bit is transmitted is set to be shorter than the predetermined period of said clock pulse generator of said third means.

9. The network system according to claim 1, wherein said fourth means comprises:

(a) fifth means for storing inhibit information on a predetermined duration for each data station on a basis of which said third means inhibits the transmission of said information bits to the synchronous signal line transmission; and

(b) sixth means for retrieving the inhibit information from said fifth means and actuating said third means to inhibit the transmission of said information bits to the synchronous signal transmission line according to the predetermined duration stored in said fifth means so that the serial data from the data station selected by said information bits is transmitted to the data transmission line within the predetermined duration.

10. The network system according to claim 9, wherein said sixth means comprises two stages of a shift register each input terminal of which is connected to said fifth means for shifting bits constituting the predetermined inhibit information so as to extend the duration for which the transmission of said information bits to the synchronous signal transmission line is inhibited by said third means.

11. The network system according to claim 10, wherein the extension of the duration is multiplified by an integer when the length of bits constituting the predetermined inhibit information and the number of stages of the shift register are increased.