Microprocessor system having a multiplexed address/data bus which communicates with a plurality of memory and input/output devices including TTL output gates

• US 4,694,394 A
• Filed: 10/10/1985
• Issued: 09/15/1987
• Est. Priority Date: 12/12/1984
• Status: Expired due to Fees

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Costantini, Giorgio
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/786,376
• Time in Patent Office: 705 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/38
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/4208 being a system bus, e.g. VME bus, Futurebus, Multibus

Abstract

A microprocessor system is disclosed wherein a microprocessor has a multiplexed address/data bus which communicates with a plurality of memory and input/output devices. A demultiplexing register permits the demultiplexing of the microprocessor address/data bus, while a decoder permits the selection of one of the system devices during a microprocessor external operation in response to the most significant address bits. The system output devices comprise a plurality of TTL outputs whose inputs are connected to the output of a demultiplexing register where, during a microprocessor external operation, information representative of the less significant address portion is latched. Datum information transfer to an output TTL gate is obtained by having an external operation executed by the microprocessor so that the most significant address bits select the gate and the less significant address portion represents the datum to be transferred.

Claims

1. A microprocessor system comprising:

a microprocessor having a first group of address lines internally connected to the output of a first address register H, a second group of multiplexed address/data lines internally and selectively connected to the output of a second address register L or of an accumulator and a plurality of control lines;

a demultiplexing register having inputs connected to said second group or multiplexed address/data lines and one of said control lines;

a control memory having address inputs connected to the outputs of said demultiplexing register and to at least one line of said first group, having information outputs connected to said second group of lines, and a selection input;

a plurality of TTL output gates provided with data inputs, one enabling input and control input connected to another one of said control lines;

a decoder having inputs connected to a subset of lines of said first group and a plurality of outputs, each of them respectively connected to the selection input of said control memory and enabling input of said TTL output gates; and

a direct connection between the outputs of said demuliplexing register and the data inputs of said TTL output gates.

2. A microprocessor system as per claim 1 characterised in that said address register L, intended to contain an address portion, is loaded with information to be transferred to one of said TTL output gates.

3. The system of claim 1 further comprising:

means for loading said address register H with an information selecting an output gate;

means for loading said address register L with the information to be transferred;

means, included in said microprocessor, for executing a fictitious memory transfer operation to the address specified by the content of said address register H and L.