VLSI programmable digital signal processor

• US 4,694,416 A
• Filed: 02/25/1985
• Issued: 09/15/1987
• Est. Priority Date: 02/25/1985
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Premerlani, William J., Hardy, Robert M., Wheeler, James E., Dunki-Jacobs, Robert J.
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US06/705,290
• Time in Patent Office: 932 Days
• Field of Search: 364/736, 364/200 MS File, 364/900 MS File
• US Class Current: 708/408
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 2207/3884 Pipelining
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters

Abstract

Method and apparatus are provided for performing a plurality of digital signal processing functions wherein each said function is a unique combination of identical subfunctions. A plurality of operating units are provided wherein each operating unit is adapted to perform one said subfunction. Apparatus and method are disclosed for programmably configuring these operating units in a variety of serial combinations wherein each combination will perform a respective signal processing function.

Claims

1. A circuit for performing different signal processing functions on digital input data, said data being in the form of binary data words, each word being presented in a bit by bit serial manner to said circuit, each of said different functions being provided by uniquely combining a series of substantially identical algebraic subfunctions performed concurrently on said input data and partially processed input data comprising:

a plurality of substantially identical algebraic digital operating units for receiving and operating on said input data to generate output data or partially processed input data, each said digital operating unit being adapted to perform said identical subfunction, and

signal directing means coupled intermediate said units for moving said input data and partially processed data into and through said units concurrently in a plurality of unique patterns, each unique pattern being associated with one of said different signal processing functions, said signal directing means being responsive to preselected user input to direct data through said plurality of units in one of said unique patterns such that said input data is operated on to generate the associated one of said plurality of functions;

said signal directing means including a plurality of data paths, configuration register means for receiving user provided configuration control signals, and multiplexer means responsive to said configuration register means for selectively coupling said data paths to said operating units to thereby direct data through said operating units in one of said patterns as determined by said user provided configuration control signals;

said multiplexer means including a plurality of multiplexer units, one of said units being associated with each of said operating units, said multiplexer units coupled to each of said data paths, each said multiplexer unit being operated to couple its associated operating unit with each of said remaining multiplexer untis via said data paths in response to said configuration control signals;

said operating units further including means for multiplying a first data word by a second data word to provide an intermediate output; and

means for adding said intermediate output to a third data word to provide a first operating unit output coupled to an associated multiplexer unit, each said operating unit further including first and second registers, said registers each having an input and an output, said inputs coupled to receive and temporarily store said first and second data words, said outputs coupled to said associated multiplexer unit to enable a delayed replica of said first and second data words to be selectively coupled to others of said operating units in accordance with said configuration control signals.

2. A circuit as recited in claim 1 wherein said signal directing means and said algebraic operating units are formed on a single integrated circuit chip.

3. The circuit recited in claim 2 further including means for directly coupling said first operating unit output to the multiplexer units associated with each adjacent operating unit.

4. The circuit recited in claim 3 further including means for directly coupling the outputs of said first and second registers to the multiplexer units associated with each adjacent operating unit.

5. A circuit as recited in claim 4 further comprising means for providing a delay beween the output of any said operating unit and the input to another said operating unit wherein said multiplexer means is further adapted to selectively couple said delay means to each of said data paths.

6. A circuit as recited in claim 4 further comprising means for truncating the data output of any of said operating units wherein said multiplexer means is further adapted to selectively couple said truncating means to each of said data paths.

7. A circuit for performing different signal processing functions on digital input data, said data being in the form of binary data words, each word being presented in a bit by bit serial manner to said circuit, each of said different functions being provided by uniquely combining a series of substantially identical algebraic subfunctions performed concurrently on said input data and partially processed input data comprising:

a plurality of substantially identical algebraic digital operating units for receiving and operating on said input data to generate output data or partially processed input data, each said digital operating unit being adapted to perform said identical subfunction;

multiplexer means associated with each unit for moving said input data and partially processed data into and through said units concurrently in a plurality of unique patterns, each unique pattern being associated with one of said different signal processing functions;

a configuration register coupled to each multiplexer, said configuration registers being serially coupled to each other in a closed loop fashion; and

input means responsive to a user for serially pre-loading a preselected binary code into said configuration registers corresponding to a preselected function to be performed by said circuit, said binary code being operative at each unit to control said associated multiplexer in directing data into and through said units to carry out said preselected function, said preselected code being available before a given operation is begun and fixed during said operation to uniquely determine the paths along which input to and outputs from each unit is directed.