Frequency divider circuit

• US 4,694,475 A
• Filed: 05/08/1986
• Issued: 09/15/1987
• Est. Priority Date: 05/18/1985
• Status: Expired due to Fees

• Current Assignee: Deutsche ITT Industries GmbH (TDK Corporation)
• Original Assignee: Deutsche ITT Industries GmbH (TDK Corporation)
• Inventors: Mehrgardt, Soenke
• Primary Examiner(s): Heyman, John S.
• Application Number:
  US06/861,152
• Time in Patent Office: 495 Days
• Field of Search: 377/47, 377/48, 377/49, 377/55, 331/1 A
• US Class Current: 377/48
• CPC Class Codes: G06F 7/68 using pulse rate multipliers or dividers pulse rate multipliers or dividers per seG06F7/70 takes precedence ; frequency division in electronic watches G04G3/02; frequency multiplication or division in oscillators H03B19/00; frequency dividing counters per se H03K23/00 - H03K29/00
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A divider-by-factor frequency divider circuit is described. The rate-multiplier principle of eliminating pulses as regularly as possible from a number of pulses of the signal to be frequency-divided is modified so that low-frequency variations in the frequency-divided signal are reduced at the expense of an increase in higher-frequency variations. This modification is achieved through the addition of a second accumulator, a pair of adders, a subtracter and a presettable counter to the accumulator of a frequency divider circuit. A rate multiplier with a coloring characteristic inverse to pink noise is thereby obtained.

Claims

1. Frequency divider circuit for divisors consisting of an integral part and a fractional part which is designed in the manner of a rate multiplier and comprises:

a digital first accumulator including a clocked data register and an m-bit first adder having a first input presented with an m-bit first digital word corresponding to the fractional part of the divisor, and having a second input fed from the output of said data register, the input of said data register being connected to the output of said first adder said first accumulator having a sum output;

an n-bit second having a first input receiving an n-bit second digital word corresponding to the integral part of said divisor and having a second input connected to the carry output of said first adder;

an n+1 bit third adder having a first input coupled to the output of said second adder, said third adder having a second input and an output;

a subtracter having its minuend input coupled to the output of said third adder output, said subtracter having a subtrahend input and an output;

a presettable counter having its preset input coupled to the output of said subtracter output, and having a count input receiving a signal to be frequency divided;

said counter having a counter output at which a pulse occurs after a number of pulses equal to the value applied to said preset input, output pulses at said counter output being the frequency-divided signal;

said frequency divided signal clocking said data register, and;

an r-bit second accumulator, wherein 1≦

r≦

m, having an input receiving the r most significant output bits of said first accumulator sum output, and having a carry output coupled to a second input of said third adder and coupled to the subtrahend input of said subtracter; and

a delay means disposed between said second accumulator carry output and said subtracter subtrahend input, said delay means having a delay equal to the period of said frequency divided signal.

2. A frequency divider circuit in accordance with claim 1, wherein said second accumulator includes:

a second clocked data register; and

an r-bit fourth adder having a first input coupled to the r most significant bits of said sum output of said first adder, a second input coupled to the output of said second data register, a sum output coupled to the input of said second data register, and a carry output connected as said second accumulator carry output.

3. A frequency divider in accordance with claim 2, wherein:

said frequency divided signal clocks said first and second data registers.

4. An adjustable frequency divider for use in a phase-locked loop, said frequency divider comprising:

a digital first accumulator having a first input receiving an m-bit first digital word corresponding to the fractional part of the divisor, said digital first accumulator having a first sum output and a first carry output;

a digital second accumulator having a first input coupled to said first sum output and receiving the r most significant bits of said first sum output, said second digital accumulator having a second sum output and a second carry output;

an n-bit second adder having a first input receiving an n-bit second digital word corresponding to the integral part of said divisor and having a second input coupled to said first carry output;

an n+1 bit third adder having a first input receiving the output of said second adder, and a second input receiving said second carry output;

delay means;

a subtracter having it minuend input coupled to the output of said third adder and its subtrahend input coupled to said second carry output by said delay means;

a presettable counter having its preset input coupled to the output of said subtracter, a count input receiving the signal to be frequency divided and an output, said counter output being the frequency divided signal.

5. An adjustable frequency divider in accordance with claim 4, wherein:

said first accumulator comprises a first adder and a first register, said first register having its input connected to said first adder output and its output connected to one of said first adder inputs;

said second accumulator comprises a second adder and a second register, said second register having its input connected to said second adder output and having its output connected to one of said second adder inputs.

6. An adjustable frequency divider in accordance with claim 4, wherein:

said counter is an up counter and said counter includes reset and enable inputs both connected to said counter output such that on the occurance of each pulse at said counter output, said counter is reset and the digital word at said preset input is transferred into said counter.

7. A frequency in accordance with claim 5, wherein:

said frequency divided signal clocks said first and second data registers.