Slave-type interface circuit operating with a series bus

• US 4,695,839 A
• Filed: 06/04/1985
• Issued: 09/22/1987
• Est. Priority Date: 06/08/1984
• Status: Expired due to Term

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Valkestijn, Leonardus, van de Kerkhof, Franciscus A. M., Barbu, Stefan
• Primary Examiner(s): Weldon, Ulysses
• Application Number:
  US06/741,090
• Time in Patent Office: 840 Days
• Field of Search: 365/233, 365/240, 365/241, 364/200, 364/382, 364/387, 364/601, 370/85, 370/99, 370/100, 340/825.04, 340/825.06, 340/825.07, 340/825.15, 375/117
• US Class Current: 340/3.21
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A slave-type interface circuit operating with a series bus in a configuration in which writing takes place after recognition of an address. A cycle transmitted by the bus contains an address sequence and a data sequence.

The circuit controls a plurality of user circuits (COM) on the basis of data stored in a memory (M) and of a decoder (CDEC).

A register (REG) and a bus logic (BUSL) receive at their inputs (L₁, L₂) information (SDA) and clock (SCL) signals. The bus logic (BUSL) receives from an identification circuit (AIC) a signal (DVA) indicating whether or not the address transmitted by the bus corresponds to an address A₀, A₁, A₂ displayed at the inputs S₀, S₁ and S₂. It controls the circuit on the basis of the register (REG) initialization signal (RST1), a signal LDS) for the authorization of the loading of data into the memory (M) and an acceptance signal (ACK) transmitted in the direction of the bus.

Claims

1. A slave type interface circuit for attaching to a serial bus having a data signal line (SDA) and a clock signal line (SCL), said circuit comprising:

a plurality of addressing inputs (S₀, S₁, S₂) for receiving present address bits (A₀, A₁, A₂) for identifying the circuit in question;

a data input connectable (L1) to said data signal line;

a clock input (L₂) connectable to said clock signal line;

a shift register (R₀ . . . R₇) connected to said data input and clock input for receiving data sequences and address sequences under synchronization by said clock signal line, said sequence being organized in bit cycles, each bit cycle having at least one sequence;

a memory (M) fed by parallel outputs of said shift register;

a first decoder (CDEC) fed by parallel outputs of said memory for generating decoded binary control signals for controlling user circuits (COM);

wherein said shift register has a downstream end output (QR₈) for forwarding an end-of-sequence acceptance signal (ACN) to a data input of a first control flip-flop (DC1) clocked by said clock signal (SCL) and whose output (Q) synchronizes a second control or pointer flip-flop (PNT), whose inverted output (P) is retrocoupled to its input (D), in which the presence of a logic level "1" at the output (Q) of the first flip-flop (DC1) and at the output (P) of the pointer flip-flop enables an initialization of the shift register, which corresponds to the return of a predetermined initial state;

said circuit furthermore having resetting means for resetting said first and second control flip-flops under the control of an end-of-cycle detection signal (SDA) after said initialization;

wherein said circuit furthermore comprises;

a logic comparator (10, 11,

     12) for comparing predetermined address bits present in said shift register (R₀ . . . R₇) and said preset address bits presented by said addressing inputs and upon correspondence producing an identification logic signal (DVA);

a storage circuit (66,

     67) for storing said identification signal, in the form of a stored identification signal (ADC);

and logical AND gate means enabling the loading into the memory (M) of the data from the shift register when both the outputs of the first control flip-flop (DC₁) and the pointer flip-flop (PNT) are in the logic state "1", and when also said stored identification signal (ADC) is present as well an end-of-sequence acceptance signal (ACN), signalling the end of a data sequence following said address sequence.

2. An interface circuit as claimed in claim 1, in which there are provided means to initialize the shift register (REG) by setting a third flip-flop of the shift register (R₀) to the state "1", and said resetting means also resets the other flip-flops (R₁ . . . R₈) of the shift register to the state "0" when the output of the first flip-flop (DC₁) is in the state "1" and the output (Q) of the pointer flip-flop (PNT) is in the state "0".

3. An interface circuit as claimed in claim 1, comprising a series of logic gates (101 . . . 109) for inhibiting the transmission of the logic signals available at the output of the first decoder (CDEC) towards the user circuits under the control of of a logic "off" signal (OFF) provided to the interface circuit.

4. An interface circuit as claimed in claim 3, comprising an auhorisation gate (90) receiving at one input the "off" signal (OFF) and at the other an output (P) from a first flip-flop (M₀) of the memory (M) loaded from the first flip-flop (R₀) of the shift register (R), so as to selectively enable the "off" signal (OFF).

5. An interface circuit as claimed in any one of the preceding claims, in which is incorporated a pulse generator (PG) which, when the circuit is switched on, generates a pulse (PON) controlling the initialization of the memory (M) and of the shift register (REG).

6. an interface circuit as claimed in claim 5, comprising a third (STR) control flip-flop and a fourth (STP) control flip-flop which, when the interface circuit is in a first state, receive at their input (D) in the clock signal (SCL) and are clocked (CK) one by the information signal (SDA) and the other by the inverse information signal (SDA), so that output (Q) of the third control flip-flop (STR) is set to the state "1" by a first type of coincidence between the clock (SCL) and information (SDA) signals corresponding to the start of a said cycle, and a fourth control flip-flop (STP) is set to the state "1" by a second type of coincidence between the clock signals (SCL) and information signals (SDA) corresponding to the end of a cycle, the third Control flip-flop (STR) being reset to zero by the inverse (SCL) of the clock signal (SCL) and the fourth control flip-flop (STP) being reset to zero by the output (Q) from the third (STR) control flip-flop, the output (Q) from the fourth control flip-flop (STP) controlling when in the logic state "1", a setting to the state "1" of the first flip-flop (R₀) of the shift register (R) and the resetting to zero of the other flip-flops (R₁ . . . R₈) of the shift register.

7. An interface circuit as claimed in claim 6, in which the fourth control flip-flop (STP) has its output set to the logic state "1" when both the stored identification signal (ADC) is at the logic state "0" and the first control flip-flop (DC₁) has its output at "1".

8. An interface circuit as claimed in claim 6, in which the shift register (REG) is initialized when the fourth control flip-flop (STP) has its output at "1".

9. An interface circuit as claimed in claim 8, in which the shift register (REG) is initialized when the third control flip-flop (STR) has its output at "1".

10. An interface circuit as claimed in claim 6, furthermore comprising a pulse generator (PG) for, upon switching-on of the circuit, generating a pulse (PON) for controlling the initialization of the memory (M) and of the shift register (REG) and also for setting the output (Q) of the fourth control flipflop (STP) to the logic state "1", which output is thereupon self-maintained in the state "1".

11. An interface circuit as claimed in claim 5, wherein the fourth control flip-flop (STP) also has its output set to the logic state "1" when both the output from the first (DC₁) control flip-flop and the second (PNT control) flip-flop and also the clock signal (SCL) are at the logic level "1".

12. An interface circuit as claimed in claim 11, in which is incorporated an acceptance flip-flop (R₉) synchronized by the clock signal (SCL) and receiving at its input the logic product of the acceptance signal (ACN) and the stored identification signal (ADC), and producing at its output an authorization signal (ACK) for transport via the data signal line.

13. An interface circuit as claimed in claim 12, in which is incorporated a pulse generator (PG) which, when the circuit is switched on, generates a pulse (PON) controlling the initialization of the memory (M) and of the shift register (REG) and which also resets to zero the acceptance flip-flop (R9).

14. An interface circuit as claimed in claim 13, in which the said pulse also resets to zero the first control flip-flop (DC₁) and sets to the state "1" the fourth control flip-flop (STP).

15. An interface circuit as claimed in claim 14, in which the circuit for storing the identification signal (DVA) comprises two inverting AND gates (66, 67) the output of one of which is retrocoupled to one of the inputs of the other and vice versa, the other input of the first of the two inverting AND gates (66) receiving the inverse (DVA) of the identification signal (DVA), but only if the pointer (PNT) has its output at the logic state "0" and if the clock signal is in the logic state "1", the other input of the second of the two inverting AND gates (67) receiving the logic product of the inverses (P) of the outputs (Q) of the third (STR) control flip-flop and the fourth (STP) control flip-flops, so as to permit maintenance, during each cycle, of the storage (ADC) of the identification signal (DVA).