Computer system comprising a data, address and control signal bus which comprises a left bus and a right bus

• US 4,695,944 A
• Filed: 09/22/1986
• Issued: 09/22/1987
• Est. Priority Date: 05/19/1982
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Zandveld, Frederik, Visser, Jeroen M.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US06/910,796
• Time in Patent Office: 365 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/105
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

A computer system comprises a bus for data, address and control signals which is divided into a left bus and a right bus by a first gating device. The gating device has an open state which is character-wise activated by a right bus request transported on the left bus. Furthermore, the gating device conducts start signals from a processor station connected to the left bus and interrupt signals from a peripheral apparatus connected to the right bus. In the closed state of the gating device, bulk data transport is possible on the right bus without interfering with the processor station. The processing speed is thus increased.

Claims

1. A computer system having a primary processor station (20) and a first random access read-write memory (22) having a first address space interconnected by a primary bus (36) for data, address signals and control signals;

said primary processor station having intercommunicating means for communicating sequentially a request signal from a prospective master station (BUSRN), then a bus allocation signal (MSN), then a "bus occupied" signal from said primary processor station (BSYN) and thereafter data signals, addres signals, master handshake signals (TMRN, TMPN) and slave handshake signals (TSMN) between an actual master station and an actual station accessed by said master station;

coupler means (34) having first interface mans (40) for interfacing to said primary bus and functioning thereto as a slave station, and second interface means (42);

a second random access read-write memory (24) having a second address space outside of said first address space, and at least one first peripheral apparatus (28) interconnected by a secondary bus (38) for data, address and control signals, said second interface means functioning as a potential master station with respect to said secondary bus;

said coupler means having, by means of inteconnection of said first and second interface means, a transmitting state for exchange of data characters, addresses, data request signals, data acknowledge signals and control signals between said primary bus and said secondary bus for executing an information exchange between a master station on said primary bus and a slave station on said secondary bus;

characterized in that;

said coupler means having static deadlock preventing means comprising unidirectionally transmitting means for transmitting initiating request signals exclusively from said primary bus to said secondary bus while blocking any transfer initiation requst signals generated by a station connected to said secondary bus;

said coupler means having alternatively to said transmitting state a non-transmitting state for allowing the coexistnece of a request on said primary bus and also data transfer between at least two stations on said secondary bus;

said second interface means for operating in a bus controller state for said secondary bus in absence of a further processor station on said secondary bus having allocation control means for exclusively controlling said secondary bus under control of a request signal (BUSRN) from said primary bus to the secondary bus;

said allocation control means having first signalling means for generating on a first bus wire a secondary bus request signal (BUSRN), second signalling means for generating on a second bus wire a secondary bus "master selected" (MSN) signal, third signalling means on a third bus wire for generating a secondary "bus occupied" signal (BSYN), fourth signalling means for generating on a fourth bus wire secondary master handshake signals (TMRN, TMPN) under the control of master handshake signals from said primary bus after allocating said secondary bus to a request signal from said primary bus; and

gating means under the control of a secondary bus slave handshake signal (TSMN) on a fifth bus wire for gating slave handshake signals (TSMN) from said secondary bus to said primary bus;

said second interface means having an alternative state to said bus controller state for operating upon presence of said further processor station on the secondary bus for relinquishing control of the "bus occupied" signal to said further processor while retaining control of said other bus allocation control and bus handshake signals; and

said coupler means are also transmissive for a start signal emanated from the primary processor station for a peripheral apparatus connected to said secondary bus and also for an interrupt signal from a peripheral connected to said secondary bus to said primary processor station.

2. A computer system as clained in claim 1, characterized in that said second interface means have a priority means for signalling a priority rank signal (OKI, OKO) to said secondary bus, said priority means having a first position for signalling upon the absence of a secondary processor station on said secondary bus a lowest priority rank to said secondary bus, but upon presence of a secondary processor (44 on said secondary bus signalling a modified priority rang higher than the rank of said secondary processor.

3. A computer system as clained in claims 1 or 2, characterized in that there is provided a second secondary bus (116) which is connected to the primary bgus via a second coupler means (114) and whereto there are connected a third random accss read-write memory (110) and a third peripheral apparatus (128), all memory locations of said read-write memories having mutally different addresses with respect to the primary bus, the second secondary bus comprising means for performing, in the closed state of the second coupler means, a second character-wise organized bulk data transport between the third read-write memory and the third peripheral apparatus.

4. A computer system as claimed in claim 1 or 2, characterized in that there is provided a subordinated secondary bus (108) which is connected to the secondary bus via a third coupler means (106) and whereto there are connected a fourth random access read-write memory (110) and a fourth peripheral apparatus (112), all emory locations of said read-write memories having mutually different addresses with respect to the primary bus, all memory locations of the second read-write memory and the fourth read-write memory having mutually different addresses with respect to the secondary bus which is directly interfaced to the primary bus, the subordinated secondary bus comprising means for performing, in the closed state of the third coupler means, a third character-wise organized bulk data transport between the fourth read-write memory and the fourth peripheral apparatus.

5. A computer system as claimed in claim 1 or 2, characterized in that a further processor station is connected to at least one said secondary bus (14).

6. A computer system as claimed in claim 5, characterized in that a second processor station is connected to the secondary bus which is connected to the primary bus by the first coupler means, the first coupler means comprising an address converter (222, 224, 228, 230) for converting a memory address received within a bus request on the primary bus as destined for the secondary bus.

7. A computer system as claimed in claim 1, wherein said primary bus and said secondary bus are fabricated to realize a short-distance data communication protocol, characterized in that said first interface means and said second interface means are realized as respective printed circuit boards with associated electronic circuit modules, and in that said interface means are interconnected by a line bundle of substantially greater length than allowable for such short distance data communication protocol.