Processor I/O and interrupt filters allowing a co-processor to run software unknown to the main processor

• US 4,695,945 A
• Filed: 02/28/1985
• Issued: 09/22/1987
• Est. Priority Date: 02/28/1985
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Irwin, John W.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Ure, Michael J.
• Application Number:
  US06/706,802
• Time in Patent Office: 936 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/36
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 15/161 Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning casings, cabinets, racks or drawers for data centers H05K5/00

Abstract

A co-processor is connectable to a main system data bus to run software unknown to the main processor. The main processor can concurrently run other software and maintains priority over shared I/O facilities by providing trapping logic incorporated in a random access memory and dynamically loadable by the master processor which contains data related to the current useability by the co-processor of a shared I/O device. Additional logic is associated with the co-processor to manage interrupts between the co-processor and the system bus.

Claims

1. In a data processing system including a main processor and at least one input/output device connected to a bus, the improvement for configuring said system to allow the addition of a co-processor to operate concurrently with said main processor and selectively sharing utilization of said input/output device, comprising:

means dynamically controlled by said main processor for selectively preventing direct access to said input/output device in response to an attempted access by said co-processor;

means connected to said means for selectively preventing for utilizing said main processor to service said attempted access of said input/output device by said co-processor when said means for selectively preventing has been enabled to prevent direct access to said input/output device by said co-processor; and

said means for selectively preventing and said main processor allowing concurrent utilization of said input/output device by said main processor and co-processor when said means for selectively preventing has not been enabled.

2. The data processing system of claim 1 wherein said input/output device further comprises a real or emulated input/output device.

3. The data processing system of claim 2 wherein said means for selectively preventing further comprises means for disconnecting said co-processor from said bus.

4. The data processing system of claim 3 wherein said means for utilizing further comprises means for saving an address of said input/output device.

5. The data processing system of claim 4 wherein said means for utilizing further comprises means for issuing an interrupt signal to said main processor.

6. The data processing system of claim 5 wherein said means for utilizing further comprises means for causing said main processor to access said input/output device corresponding to said saved address and read data from said input/output device.

7. The data processing system of claim 6 wherein said means for utilizing further comprises means for causing said co-processor to be temporarily reconnected to a portion of said bus and means for causing said main processor to communicate said data read from said input/output device to said co-processor.

8. The data processing system of claim 7 wherein said portion of said bus is a data portion of said bus.

9. The data processing system of claim 6 wherein said means for utilizing further comprises means for causing said main processor to access said input/output device corresponding to said saved address and write data to said input/output device.

10. The data processing system of claim 9 wherein said means for utilizing further comprises means for causing said co-processor to be temporarily reconnected to a portion of said bus and means for causing said co-processor to communicate said data to be written from said co-processor to said main processor.

11. The data processing system of claim 10 wherein said portion of said bus is a data portion of said bus.

12. The data processing system of claim 1 further comprising means controllable by said main processor for selectively creating a simulated interrupt from data on a data portion of said bus and for causing this created interrupt to be sent to said co-processor.

13. In a data processing system including a main processor and at least one input/output device connected to a bus, the method for configuring said system to allow the addition of a co-processor capable of operation concurrent with that of said main processor and selectively sharing utilization of said input/output device, comprising:

selectively preventing direct access to said input/output device by said co-processor;

utilizing said main processor to service an attempted access of said input/output device by said co-processor when said direct access to said input/output device by said co-processor has been selectively prevented; and

allowing concurrent utilization of said input/output device by said main processor and co-processor when said direct access to said input/output device is not being selectively prevented.

14. The method of claim 13 wherein said step of selectively preventing further comprises utilizing said main processor dynamically to selectively prevent access by said co-processor to said input/output device.

15. The method of claim 14 wherein said step of selectively preventing further comprises disconnecting said co-processor from said bus.

16. The method of claim 15 wherein said step of utilizing further comprises saving an address of said input/output device.

17. The method of claim 16 wherein said step of utilizing further comprises issuing an interrupt signal to said main processor.

18. The method of claim 17 wherein said step of utilizing further comprises causing said main processor to access said input/output device corresponding to said saved address and read data from said input/output device.

19. The method of claim 17 wherein said step of utilizing further comprises causing said main processor to access said input/output device corresponding to said saved address and write data to said input/output device.

20. The method of claim 13 further comprising utilizing said main processor dynamically to selectively create a simulated interrupt from data on a data portion of said bus and cause this created interrupt to be sent to said co-processor.