Apparatus for reducing test data storage requirements for high speed VLSI circuit testing

• US 4,696,005 A
• Filed: 06/03/1985
• Issued: 09/22/1987
• Est. Priority Date: 06/03/1985
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Visco, Gary P., Moser, John J., Shushereba, John J., Millham, Ernest H.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/740,592
• Time in Patent Office: 841 Days
• Field of Search: 371/20, 371/25, 371/27, 324/73 R, 324/73 AT, 324/73 PC
• US Class Current: 714/743
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31921 using compression techniques, e.g. patterns sequencer

Abstract

Apparatus for applying for a plurality of test cycles data specifying a plurality of test conditions to a multiple pin electronic circuit. A random access memory includes at a plurality of higher order addresses a complete data field for a plurality of test cycles. Some of said data fields include an operational code indicating that a minority of data bits in a field are to change in a consecutive number of following test cycles. A hold register is connected to receive each addressed row of test data from the memory. The higher order addresses of a memory addressed to produce complete data fields in the hold register. An operational code will be decoded to indicate a number of subsequent consecutive test cycles where a minority of data in the hold register are to be changed. The lower order addresses of the memory are subsequently addressed for a number of consecutive test cycles indicated by the operational code. The data contained in the lower order memory addresses is inserted in the hold register without changing the contents of a majority of hold register data bits.

Claims

1. In an automatic testing system, apparatus for supplying test data for a plurality of test cycles identifying test conditions for a multipin electronic circuit, comprising:

a random access memory having a plurality of higher order addresses identifying a plurality of memory rows containing a complete field of test data, some of said rows containing an operational code specifying a number of subsequent test cycles over which a minority of data in said rows are to change without changing the remaining data of the row, and having a smaller number of lower order addresses which contain data in the same position within the data field as said minority of data;

means for sequentially addressing each of said higher order addresses;

a repeat buffer for sequentially addressing said lower order addresses;

a hold register for receiving each row of addressed data in said memory and for outputting test data identifying test conditions for a multipin electronic circuit; and

processor means for indexing said means for sequentially addressing said higher order addresses and decoding each operational code received in said holding register, said processor connected to inhibit addressing by said means for sequentially addressing said higher order addresses and addressing said repeat buffer for a number of test cycles identified by said operational code whereby only said minority of data bits in said holding register having a field position corresponding to data bits in said lower order memory address change.

2. In an automatic tester for applying test data identifying test conditions to a multipin electronic circuit and determining the circuit response to said test conditions an apparatus for supplying test data for each of said cycles, comprising:

a random access memory having a first plurality of rows of data fields representing sequential test conditions for said pins, some of said rows including an operational code indicating a number of test cycles that a minority of said data in said row is to be changed, a second plurality of rows of data fields of the same length as said first plurality of rows, containing a minority of data bits to replace said minority of data for subsequent test cycles and containing data indicating the remaining data of a previously addressed row is to remain the same;

a hold register connected to receive the output of said memory and for outputting test data identifying test conditions for a multipin electronic circuit;

first and second addressing registers connected to address said first plurality of rows of data and said second plurality of rows of data;

a repeat buffer means connected to said second addressing register, said repeat buffer means including the address of subsequent test cycle data in said second plurality of rows of data; and

,

processor means connected to sequentially address said first plurality of rows whereby each of said first rows is sequentially loaded into said hold register, said processor means including means for decoding an operational code in said hold register and addressing said repeat buffer for a subsequent number of test cycles indicated by said operational code, whereby said minority of data from said second plurality of rows of bits are substituted for a minority of data bits in said hold register; and

,

the contents of a majority of test data bits in said hold register are held constant during a subsequent number of test cycles identified by said operational code.

3. In an automatic testing system, apparatus for applying a plurality of test cycles, data specifying a plurality of test conditions to a multiple pin electronic circuit for determining a response to said test conditions comprising:

a random access memory having a plurality of memory rows for storing data in a field, the higher order addresses of said memory including complete cycles of test data and an operational code, and a minority of lower order addresses including less than a complete test data field of the most frequently changing data common to many of said test cycles;

a hold register connected to receive each addressed row of test data in said memory and for outputting test data identifying test conditions for a multipin electronic circuit;

means for addressing each of said higher order addresses in sequence, whereby complete data fields of said memory are loaded in said hold register as well as an operational code which indicates a number of subsequent consecutive test cycles where a minority of said hold register data bits are to be changed; and

,

sequentially addressed second memory means for addressing said lower order memory addresses for a number of test cycles specified by said operational code, whereby said most frequently changing data is received in said holding register without changing the contents of said majority of data bits in said hold register.

4. An automatic testing system, apparatus for applying test data identifying test conditions to a multipin electronic circuit for determining a response to said test conditions comprising:

a random access memory having a plurality of higher order addresses identifying a plurality of memory rows containing a complete field of test data, some of said rows containing an operational code specifying a number of consecutive test cycles in which a minority of data in said field of test data is to change, and having in a smaller number of lower order addresses data in the same position of said field of test data as said minority of data;

a hold register for receiving each of said rows of test data and operation codes and for outputting test data identifying test conditions for a multipin electronic circuit;

a source of pulses corresponding to each test cycle;

a high order memory address register connected to address in sequence said higher order memory addresses in response to each of said pulses;

a counter connected to receive a count indicating the number of consecutive test cycles specified by said operational code, said counter connected to inhibit said higher order address register when a non-zero count is present and connected to be decremented in response to said test cycle pulses;

a repeat buffer means connected to be addressed by each of said pulses when said counter indicates a non-zero count, said repeat buffer including a sequence of lower order addresses of said random access memory which contain consecutive test cycle data to be substituted for said minority of test data;

an address register connected to address said lower order addresses in response to said repeat buffer output; and

processor means connected to decode an operational code produced when said random access memory contents are received in said hold register, and connected to provide a count to said counter indicating the number of test cycles in which only said minority of test data are to be changed, whereby each succeeding pulse corresponding to a test cycle results in said repeat buffer addressing said memory replacing said minority of data in said hold register with data from said lower order addresses until said counter decrements to zero.

5. In a system for testing multipin LSSD integrated circuit structure, wherein data is produced for each test cycle defining a condition for each pin of an integrated circuit, an apparatus for producing test data for each test cycle of said integrated circuit comprising:

a programmable memory having a first group of row addressable memory locations containing a field of test data defining test conditions for each of said pins, some of said first group of memory locations of a row including an operational code defining a number of consecutive test cycles where only a minority of data bits of an associated data field are to change, a second group of row addressable memory locations containing data bits which have a position in said rows corresponding to the position of said minority of data bits;

a hold register connected to receive a row of data from said memory and apply data corresponding to said field of test data to said integrated circuit;

a first address register connected to address said higher order memory locations in sequence, whereby data from each of said higher order locations is inserted in said hold register;

a repeat buffer including a number of sequential memory locations containing a series of said lower order addresses of said memory containing data bits;

a second address register connected to address said memory in response to a data signal from said repeat buffer; and

processor means connected to increment said first address register, whereby said higher order memory locations are addressed, said processor connected to detect an operational code in said hold register and to store a number defining a number of consecutive test cycles, said processor means inhibiting said first address register from incrementing during said number of consecutive test cycles, and reading from said repeat buffer for said number of test cycles said stored lower order addresses, whereby said memory contents in said second group of memory locations are applied to said hold register.

6. The apparatus of claim 5 wherein the remaining data positions in said second group of memory locations have a second group of data bits which identify bit locations in said hold register which do not change during said number of consecutive test cycles.

7. The apparatus of claim 5 wherein said minority of data bits represent the test conditions for input and output terminals SI, SO of an LSSD structure.

8. The apparatus of claim 5 wherein said first group of row addressable locations include a field of test data, a majority of data in each field corresponding to combinational logic conditions for a majority of said LSSD integrated circuit pins, and said minority of data corresponding to input/output logic conditions for a minority of said pins.

9. The apparatus of claim 6 wherein said hold register includes decoding circuitry which inhibits changing data in locations corresponding to said second group of data bits in said second group of data bits in said second group of memory locations.