Transistor having a superlattice

• US 4,697,197 A
• Filed: 10/11/1985
• Issued: 09/29/1987
• Est. Priority Date: 10/11/1985
• Status: Expired due to Fees

• Current Assignee: RCA Corporation
• Original Assignee: RCA Corporation
• Inventors: Dresner, Joseph
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US06/786,888
• Time in Patent Office: 718 Days
• Field of Search: 357/4 SL, 357/4, 357/23.2, 357/23.7, 357/16
• US Class Current: 257/16
• CPC Class Codes: H01L 29/154 comprising at least one long range structurally disordered material, e.g. one-dimensional vertical amorphous superlattices
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A transistor has a superlattice in the channel region. The superlattice has alternate interleaved layers of undoped wide and narrow bandgap materials with the layers extending in a direction parallel to the channel region. Preferably a narrow band gap layer is adjacent a gate insulator to provide maximum increase in mobility.

Claims

1. A transistor comprising:

spaced source and drain regions with a channel region therebetween;

said channel region comprising a gate electrode, and a superlattice spaced apart by a gate insulator, said superlattice having a plurality of undoped interleaved wide and narrow bandgap layers, said layers extending between the source and drain regions.

2. The transistor of claim 1, wherein the superlattice comprises a narrow band gap layer disposed adjacent said gate insulator.

3. The transistor of claim 1, wherein said gate electrode is disposed on one side of said supperlattice, and said source and drain regions each include an electrode disposed adjacent the opposite side of said superlattice remote from said gate electrode.

4. The transistor of claim 3, wherein said source and drain regions each include electrodes disposed on a substrate.

5. The transistor of claim 3, wherein said gate electrode is disposed on a substrate.

6. The transistor of claim 1, wherein said narrow band gap layers each have a thickness between about 3 and 15 nanometers.

7. The transistor of claim 6, wherein said narrow bandgap layers have a thickness no greater than about 6 nanometers.

8. The transistor of claim 7, wherein said wide bandgap layers have a thickness of about 10 nanometers.

9. The transistor of claim 8, wherein said wide and narrow bandgap layers have a bandgap difference of at least 100 millielectron-volts therebetween.

10. The transistor of claim 1, wherein said narrow bandgap layers each comprise an amorphous material selected from the group consisting of silicon, hydrogenated silicon, and a hydrogenated silicon-germanium alloys.

11. The transistor of claim 10, wherein said wide bandgap layers each comprise an amorphous hydrogenated material selected from the group consisting of a silicon-carbon and a silicon-nitrogen alloys.

12. The transistor of claim 11, wherein said wide and narrow bandgap layers have a bandgap difference of at least 100 millielectron-volts therebetween.

13. The transistor of claim 1, wherein said wide bandgap layers have a thickness of about 10 nanometers.

14. The transistor of claim 1, wherein said wide bandgap layers comprise an amorphous hydrogenated material selected from the group consisting of a silicon-carbon and a silicon-nitrogen alloys.

15. The transistor of claim 1, wherein said superlattice has a thickness between about 50 and 250 nanometers.

16. The transistor of claim 1, wherein said superlattice comprises between about 5 and 30 pairs of narrow and wide bandgap layers.

17. The transistor of claim 1, wherein said narrow bandgap layers have a thickness no greater than about 6 nanometers.

18. The transistor of claim 1, wherein said wide and narrow bandgap layers have a bandgap difference of at least 100 millielectron-volts therebetween.