Hardware logic simulator
First Claim
1. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:
- (a) a plurality of harware gates, each of which corresponds to and emulates a logic element in said circuit, each hardware gate having an output and at least two inputs;
(b) interconnnection means selectively operable for establishing a connection between the output of a given hardware gate and an input of any other hardware gate including said given gate; and
(c) multiplex means for operating said interconnection means and determining which, and when, each connection is made.
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Accused Products
Abstract
Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprises a plurality of hardware gates, each of which is programmable so as to correspond to and emulate an element in said logic circuit. Each hardware gate has an output and at least two inputs. A selectively operable interconnection system is provided for establishing a connection between the output of any hardware gate and an input of any hardware gate. A multiplexing system is also provided for operating the interconnection system and determining which, and when, each connection is made between the output of any hardware gate and an input of any hardware gate.
132 Citations
39 Claims
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1. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:
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(a) a plurality of harware gates, each of which corresponds to and emulates a logic element in said circuit, each hardware gate having an output and at least two inputs; (b) interconnnection means selectively operable for establishing a connection between the output of a given hardware gate and an input of any other hardware gate including said given gate; and (c) multiplex means for operating said interconnection means and determining which, and when, each connection is made. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:
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(a) a plurality of hardware gates, each of which corresponds to and emulates a logic element in said circuit, each hardware gate having an output and at least two inputs; (b) interconnection means selectively operable for establishing a connection between the output of any hardware gate and the input of any hardware gate; and (c) multiplex means for operating said interconnection means and determining which, and when, each interconnection is made; (d) said multiplex means establishing the output to, and the input of the apparatus, said multiplex means being constructed and arranged to establish temporarily limited connections between said hardware gates according to a schedule upon the completion of which the apparatus will have produced outputs corresponding to the output of said logic circuit for each possible input thereto; (e) said multiplex means including as time slot counter for producing time slot signals that establish a plurality of time slots within which said temporally limited connections are made; (f) said interconnection means including an input selector associated with the inputs of each hardware gate, and an input bus having a plurality of input bus lines, said input selector being constructed and arranged for selectively connecting the input of a hardware gate to, or selectively disconnecting the input from, any one of said input bus lines of said input bus; and (g) wherein the number of input lines is equal to the number of output lines.
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12. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:
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(a) a plurality of hardware gates, each of which corresponds to and emulates a logic element in said circuit, each hardware gate having an output and at least two inputs; (b) interconnection means selectively operable for establishing a connection between the output of any hardware gate and the input of any hardware gate; and (c) multiplex means for operating said interconnection means and determining which, and when, each interconnection is made; (d) said multiplex means establishing the output to, and the input of the apparatus, said multiplex means being constructed and arranged to establish temporally limited connections between said hardware gates according to a schedule upon the completion of which the apparatus will have produced outputs corresponding to the output of said logic circuit for each possible input thereto; (e) said multiplex means including as time slot counter for producing time slot signals that establish a plurality of time slots within which said temporally limited connections are made; (f) said interconnection means including an input selector associated with the inputs of each hardware gate, and an input bus having a plurality of input bus lines, said input selector being constructed and arranged for selectively connecting the input of a hardware gate to, or selectively disconnecting the input from, any one of said input bus lines of said input bus; and (g) wherein said input selector includes, for each input to a hardware gate, selectively operable means by which such input can be connected to or disconnected from an input bus line. - View Dependent Claims (13, 14, 15)
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16. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:
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(a) a plurality of hardware gates, each of which corresponds to and emulates a logic element in said circuit, each hardware gate having an output and at least two inputs; (b) interconnection means selectively operable for establishing a connection between the output of any hardware gate and the input of any hardware gate; and (c) multiplex means for operating said interconnection means and determining which, and when, each interconnection is made; (d) said multiplex means establishing the output to, and the input of the apparatus, said multiplex means being constructed and arranged to establish temporally limited connections between said hardware gates according to a schedule upon the completion of which the apparatus will have produced outputs corresponding to the output of said logic circuit for each possible input thereto; (e) said multiplex means including as time slot counter for producing time slot signals that establish a plurality of time slots within which said temporally limited connections are made; and (f) wherein said interconnection means includes an output distributor associated with with the output of each hardware gate, and an output bus having a plurality of output lines, said output distributor being constructed an arranged for selectively connecting the output of a hardware gate to, or selectively disconnecting the output from, any one of said lines of said output bus. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. Apparatus for verifying the design of a logic circuit composed of a plurality of interconnected logic elements comprising:
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(a) a plurality of level 0 modules each of which comprises a plurality of hardware gates having inputs and outputs and individually corresponding to and emulating different logic elements of said logic circuit; (b) a level 0 output bus having a plurality of output bus lines that correspond to a plurality of input bus lines of a level 0 input bus; (c) an output distributor associated with each hardware gate for establishing connections between the outputs of the hardware gates and the output bus line of the level 0 output bus; (d) an input selector associated with each hardware gate for establishing connections between inputs to the hardware gates and the input bus lines of the level 0 input bus; and (e) an input/output buffer for selectively connecting output bus lines of a level 0 output bus to corresponding input bus lines of the level 0 input bus. - View Dependent Claims (35, 36, 37, 38, 39)
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Specification