Stacked complementary metal oxide semiconductor inverter

• US 4,698,659 A
• Filed: 05/16/1986
• Issued: 10/06/1987
• Est. Priority Date: 05/31/1982
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Mizutani, Yoshihisa
• Primary Examiner(s): Carroll, J.
• Application Number:
  US06/865,652
• Time in Patent Office: 508 Days
• Field of Search: 357/23.1, 357/42, 357/59, 357/67, 357/71, 357/23.7, 357/4
• US Class Current: 257/69
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An MOS transistor of second conductivity type is provided which is formed in a semiconductor substrate of first conductivity type and includes a first source region of second conductivity type, a first drain region of second conductivity type, and a gate electrode provided on a gate insulation layer. Further, an MOS transistor of first conductivity type is provided which is stacked on the MOS transistor of second conductivity type and includes a second source region, a second drain region and the gate electrode. The first and second source regions are connected to each other through a conductive layer which is selected from a given metal layer and a given metal silicide layer.

Claims

1. A stacked CMOS (Complementary Metal Oxide Semiconductor) inverter comprising:

a semiconductor substrate of a first conductivity type;

an MOS transistor of a second conductivity type including a first source region and a first drain region, which are of said second conductivity type, provided in one of the surface regions of said semiconductor substrate to form a first channel region, a first insulation layer provided on said first channel region, and a gate electrode provided on said first insulation layer;

a second insulation layer for covering the surfaces of said gate electrode, said first source region and said first drain region;

an MOS transistor of said first conductivity type including a semiconductor layer formed on said second insulation layer which has a portion facing said gate electrode and serving as a second channel region, a portion facing said first source region and serving as a second source region of said first conductivity type, and a portion facing said first drain region and serving as a second drain region of said first conductivity type, and said gate electrode, with said second insulation layer, interposed between said gate electrode and said second channel region, being used as a gate insulation layer;

first, second and third connection electrode means for connecting said first and second source regions, said first drain region, and second drain region, respectively, to an exterior circuit;

means for electrically connecting together said first and second source regions while precluding formation of a parasitic diode between said first source region and said first connection electrode means comprising a first conductive layer of a metal silicide interposed directly between said first and second source regions, said first conductive layer covering the entire surface of said first source region, and said source region directly contacting said first conductive layer through a contact hole provided in said second insulating layer; and

a second conductive layer, which is comprised of the same material as said first conductive layer, covering the entire surface of said first drain region.

2. A stacked CMOS inverter according to claim 1, wherein said first conductive layer is selected from PtSi (platinum silicide), MoSi (molybodenum silicide), WSi (tungsten silicide), and PdSi (palladium silicide).

3. A stacked CMOS inverter according to claim 1, wherein said first connection electrode means is directly connected to said first conductive layer.

4. A stacked CMOS inverter according to claim 1, wherein said first connection electrode means is directly connected to said second source region.