Inverter apparatus

• US 4,698,744 A
• Filed: 03/19/1985
• Issued: 10/06/1987
• Est. Priority Date: 03/26/1984
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Tokizaki, Hisashi, Katsuki, Hikaru, Ohkubo, Katsuhiro, Ohtsuka, Nobuo, Itani, Kiyoshi, Funagoshi, Tomohide
• Primary Examiner(s): RUGGIERO, JOSEPH F
• Application Number:
  US06/713,479
• Time in Patent Office: 931 Days
• Field of Search: 364/130, 364/400, 364/140, 364/557, 364/505, 364/506, 364/483, 364/492, 318/801, 318/802, 318/803, 318/807, 318/810, 318/811, 318/254, 318/138, 363/41, 363/55, 363/56, 363/98, 363/132, 363/137, 165/13, 165/14, 165/17
• US Class Current: 700/12
• CPC Class Codes: G05B 19/0423 Input/output

Abstract

An inverter apparatus comprises a bridge circuit composed of a combination of a plurality of switching transistors and a microprocessor controlling turning on and turning off of these switching transistors. Patterns of combinations of ON and OFF states of respective switching transistors obtained based on the theory of PWM (pulse width modulation) are stored in a first ROM of microprocessor. Transition of the pattern for each range of 0°-30° in electrical angle is stored in a second ROM in the sequence of periods subdivided from the range. Data of the time during which the pattern to be held for each period is stored in a third ROM. The microprocessor sets the holding time data in a timer, and also outputs the ON/OFF pattern, thereby turning on or turning off of each switching transistor is controlled in accordance with the count of this timer and the ON/OFF pattern. By repeating this cycle, a switching signal which continues during one cycle of AC (range of 0°-360° in electrical angle) is given to each switching transistor. Accordingly, an AC output by the PWM system is obtainable from the bridge circuit.

Claims

1. An inverter apparatus for providing a periodic output signal, comprising:

a bridge circuit having a plurality of switching elements each coupled to selectively transmit to an output thereof a first signal level when said switching element is an ON state and a second signal level when it is in an OFF state,

first memory means for storing pattern data of combinations of ON state and OFF state of said respective switching elements obtained based on the PWM theory,

time data outputting means for outputting time data corresponding to each said combination of said first memory means, said time data including ON time data defining the time during which said ON state of said respective switching elements is maintained and OFF time data defining the time during which said OFF state of said respective switching elements is maintained, and

switching signal outputting means responsive to said pattern data and said time data for outputting switching signals to said switching elements, said outputting means including means for selecting for said switching signal a sequence of said pattern data combinations calculated to define a cycle of said output signal for the inverter and means for maintaining each of said pattern data combinations for a time defined by the corresponding time data, whereby the period of the output AC signal cycle defined by said sequence of pattern data combinations can be made to correspond to different frequencies, said switching signals being applied to the respective switching elements of said bridge circuit from which an AC output is outputted, the frequency of said AC output being determined over the entire operating frequency range of the inverter by the total time data of said ON time data and said OFF time data is one cycle.

2. An inverter apparatus in accordance with claim 1, wherein said switching signal outputting means includes a timer means for controlling the holding time of said switching signal based on said time data.

3. An inverter apparatus in accordance with claim 2, wherein said first memory means stores in advance said pattern data for each of plural periods, and said time data outputting means outputs said time data during at least one AC cycle for each of said plural periods.

4. An inverter apparatus in accordance with claim 3, wherein said time data outputting means includes a second memory means for storing in advance said time data for each of said plural periods.

5. An inverter apparatus in accordance with claim 3, wherein said time data outputting means includes a calculating means for calculating to evaluate said time data for at least one of said plural periods.

6. An inverter apparatus in accordance with claim 5, which further comprises a third memory means for storing in advance predetermined numeric values for calculation by said calculating means, and wherein

said calculating means calculates to evaluate said time data based on said predetermined numerical values.

7. A inverter apparatus in accordance with claim 6, wherein said second memory means stores in advance initial values as said time data, and said calculating means calculates to evaluate time data based on said initial values and said predetermined numeric values.

8. An inverter apparatus in accordance with claim 5, wherein said time data outputting means outputs different data according to the ratio of output voltage to output frequency V/F.

9. An inverter apparatus in accordance with claim 8, wherein said third memory means stores said initial value for each V/F.

10. An inverter apparatus in accordance with claim 2, wherein said switching signal outputting means includes a microprocessor, and said microprocessor performs other controls during timer operation by said timer means.

11. An inverter apparatus in accordance with claim 10, which further comprises an air-conditioning system including a motor driven by output from said bridge circuit, and wherein

said microprocessor controls defrosting operation of said air-conditioning system during timer operation by said timer means.

12. An inverter apparatus for providing a periodic output signal which is employed for a refrigerant circuit comprising at least an evaporator, which comprises

a bridge circuit which includes a plurality of switching elements, each coupled to selectively transmit to an output thereof a first signal level when said switching element is an ON state and a second signal level when it is in an OFF state,

first memory means which stores pattern data of combinations of ON/OFF states of said respective switching elements obtained based on the PWM theory,

second memory means which stores time data corresponding to each said pattern combination of said first memory means and representative of the holding time during which said pattern combination is to be held, and

a switching signal outputting means which outputs switching signals to said switching elements based on said pattern data from said first memory means and output of said timer means, and controls defrosting of said evaporator during time-counting operation of said timer means, said outputting means including means for selecting for said switching signal a sequence of said pattern data combinations calculated to define a cycle of said output signal for the inverter and means for maintaining each of said pattern data combinations for a time defined by the corresponding time data, whereby the period of the output AC signal cycle defined by said sequence of pattern data combinations can be made to correspond to different frequencies.