Security for integrated circuit microcomputer with EEPROM

• US 4,698,750 A
• Filed: 12/27/1984
• Issued: 10/06/1987
• Est. Priority Date: 12/27/1984
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Raghunathan, Kuppuswamy, Wilkie, Brian F., Suchyta, John, Gallup, Michael
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Fairbanks, Jonathan C.
• Application Number:
  US06/686,785
• Time in Patent Office: 1,013 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 365/185, 365/218, 365/228, 365/229, 365/104
• US Class Current: 365/185.04
• CPC Class Codes: G06F 12/1433 for a module or a part of a module

Abstract

An integrated circuit microcomputer with EEPROM has a limited number of modes for operation. In at least first and second modes, the inner workings of the microcomputer, including the contents of the EEPROM, can be read externally from the microcomputer. An EEPROM security bit, when set, prevents the first mode from being entered and causes the EEPROM to be erased when the second mode is entered. The EEPROM is also erased if the security bit is erased.

Claims

1. In an integrated circuit microcomputer having on-board memory including an EEPROM and having detection means for detecting a request for a mode of operation of the microcomputer and characterized as having a first mode of operation in which contents of the EEPROM can be read externally from the microcomputer, and a second mode of operation in which the contents of the EEPROM cannot be externally read from the microcomputer, means for securing the contents of the on-board memory, comprising:

an EEPROM security bit which can be set after the EEPROM has been loaded and which is erasable only if the EEPROM is also erased; and

first means, coupled to the detection means, for erasing the contents of the EEPROM in response to the detection means receiving a request for the first mode of operation when the security bit is set.

2. The microcomputer of claim 1, wherein the first means erases the security bit after the EEPROM has been erased.

3. The microcomputer of claim 2 further having an on-board RAM, wherein the first means erases the RAM in response to entering the first mode of operation when the security bit is set.

4. The microcomputer of claim 3 further having a third mode of operation in which the contents of the EEPROM can be read externally from the microcomputer, wherein the means for securing the contents of the on-board memory further comprises:

second means for preventing the microcomputer from entering the third mode of operation when the security bit is set.

5. The microcomputer of claim 1 further having a third mode of operation in which the contents of the EEPROM can be read externally from the microcomputer, wherein the means for securing the contents of the on-board memory further comprises:

second means for preventing the microcomputer from entering the third mode of operation when the security bit is set.

6. The microcomputer of claim 5, wherein the first means erases the security bit after the EEPROM has been erased.

7. In an integrated circuit microcomputer having on-board memory including an EEPROM and having detection means for detecting a request for a mode of operation of the microcomputer and characterized as having a first mode of operation in which contents of the EEPROM can be read externally from the microcomputer, and a second mode of operation in which the contents of the EEPROM cannot be read externally from the microcomputer, a method of securing the contents of the on-board memory, comprising:

providing an EEPROM security bit which can be set after the EEPROM has been loaded;

loading the EEPROM;

setting the security bit; and

erasing the EEPROM in response to the detection means receiving a request for the first mode of operation.

8. The method of claim 7 further comprising:

erasing the security bit after the EEPROM has been erased.

9. The method of claim 8 further comprising:

checking the EEPROM to verify that it has been erased before erasing the security bit; and

preventing the erasure of the security bit if any of the EEPROM which was checked was not erased.

10. The method of claim 9 futher comprising:

providing the microcomputer with a third mode of operation in which the contents of the EEPROM can be externally read; and

preventing the microcomputer from entering the third mode of operation when the security bit is set.

11. The method of claim 10 further comprising:

providing an on-board RAM; and

erasing the RAM in response to entering the first mode of operation when the security bit is set.

12. In an integrated circuit microcomputer having on-board memory including an EEPROM and a ROM and having detection means for detecting a request for a mode of operation of the microcomputer and characterized as having a first mode of operation in which contents of the EEPROM can be read externally from the microcomputer, and a second mode of operation in which the contents of the EEPROM cannot be read externally from the microcomputer, a method of securing the contents of the on-board memory, comprising:

providing an EEPROM security bit which can be set after the EEPROM has been loaded;

loading the ROM with a program which causes the microcomputer to erase the EEPROM in response to the detection means receiving a request for the first mode of operation.

13. The method of claim 12 wherein the program loaded into the ROM is further characterized as causing the microcomputer to erase the security bit after the EEPROM has been erased.

14. In an integrated circuit microcomputer having on-board memory including an EEPROM and having detection means for detecting a request for a mode of operation of the microcomputer and characterized as having a first mode of operation in which contents of the EEPROM can be read externally from the microcomputer and a second mode of operation in which the contents of the EEPROM cannot be read externally from the microcomputer, means for securing the contents of the on-board memory comprising:

an EEPROM security bit which can be set after the EEPROM has been loaded;

a ROM containing a program which causes the microcomputer to erase the EEPROM in response to the detection means receiving a request for the first mode of operation when the security bit is set.

15. The microcomputer of claim 14 wherein the ROM is further characterized by the program therein causing the microcomputer to erase the security bit after the EEPROM has been erased.

16. The microcomputer of claim 15 further having an on-board RAM, wherein the ROM is further characterized by the program therein causing the microcomputer to erase the RAM in response to entering the first mode when the security bit is set.

17. The microcomputer of claim 16 further having a third mode of operation in which the contents of the EEPROM can be read externally, wherein the means for securing the contents of the on-board memory further comprises:

means for preventing the microcomputer from entering the third mode of operation when the security bit is set.

18. The microcomputer of claim 14 further having a third mode of operation in which the contents of the EEPROM can be read externally, wherein the means for securing the contents of the on-board memory further comprises:

means for preventing the microcomputer from entering the third mode of operation when the security bit is set.

19. The microcomputer of claim 18 wherein the ROM is further characterized by the program therein causing the microcomputer to erase the security bit after the EEPROM has been erased.