Method of optimizing signal timing delays and power consumption in LSI circuits

• US 4,698,760 A
• Filed: 06/06/1985
• Issued: 10/06/1987
• Est. Priority Date: 06/06/1985
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines SA (International Business Machines Corporation)
• Inventors: Williams, Robert R., Lembach, Robert F., Lewis, Steven D.
• Primary Examiner(s): Krass, Errol A.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/741,922
• Time in Patent Office: 852 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/569
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

A method of optimizing signal timing delays and power consumption through multi-path LSI circuits constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power levels which are selectable to control the timing delays through the circuit block, wherein the method steps include the formation of a power-performance derivative for each circuit block, identifying therefrom the relative contribution to signal delay of the circuit block in the entire multi-path configuration, and selecting the optimum power level for an overall multi-path minimum signal delay condition, through a process of iterative calculation of timing delays through individual circuit blocks and multi-path timing analysis.

Claims

1. A method of optimizing signal timing delays and power consumption through multi-path LSI circuit networks constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of selectable power drive levels which determine circuit block signal timing delays, the objective of the method being to reduce an LSI circuit network signal timing delay to less than a predetermined maximum signal timing delay while at the same time achieving the lowest LSI circuit network power consumption consistent therewith, comprising the steps of

(a) determining the timing delays and power consumption characteristics of each circuit block for all of the plurality of power drive levels;

(b) calculating the timing delays, at a first power drive level, through all of the circuit blocks and determining the circuit network timing delays by summing circuit block timing delays through the multi-path circuit network;

(c) calculating a "slack time" value for each circuit block by subtracting the circuit network timing delays from the maximum permissible circuit network timing delays, and allocating this difference as a "slack time" value for each circuit block according to its relative timing delay through the multi-path circuit network;

(d) calculating a "lateness time" value for each of the circuit blocks by summing the circuit block "slack time" values through the multi-path network of circuit blocks which contribute to circuit network timing delays;

(e) repeating step (b)-(d) at a second power drive level;

(f) forming a performance derivative for each circuit block by subtracting the second power drive level "lateness time" value from the first power drive level "lateness time" value, and dividing the result by a denominator formed by subtracting the second power drive level power consumption from the first power drive level power consumption;

(g) identifying the circuit blocks having the highest performance derivatives, and setting the power drive level of at least one of such circuit blocks to the second level while returning the remaining circuit blocks to the first power drive level;

(h) repeating the steps (b)-(g) by substituting the power drive level selected in step (g) for the original first power drive level, and substituting an incrementally increased power drive level for each circuit block for the second power drive level, until all circuit blocks "lateness time" values are reduced to substantially zero; and

(i) physically implementing in the LSI circuit network the power drive levels of each circuit block as determined from step (h) as the operable power drive levels of each of the circuit blocks.

2. The method of claim 1, wherein the step (g) of identifying the circuit blocks having the highest performance derivatives further comprises identifying only one circuit block.

3. The method of claim 1, wherein the step (g) of identifying the circuit bocks having the highest performance derivatives further comprises identifying n % of said circuit blocks, where n is a nonzero number.

4. The method of claim 1, wherein the step (e) of repeating at a second power drive level further comprises repeating at the next highest incremental power drive level.

5. The method of claim 4, wherein the step (g) of identifying the circuit blocks having the highest performance derivatives further comprises identifying n % of said circuit blocks, where n is a nonzero number.

6. A method of optimizing signal timing delays through multi-path LSI circuit networks constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power drive levels which are selectable for controlling the timing delays through the circuit block, wherein the method of optimizing further comprises reducing the network signal timing delays to less than predetermined maximum permissible network signal timing delays at the lowest obtainable network power consumption, comprising the steps of

(a) initializing all circuit block power drive levels to their respective lowest levels;

(b) determining the signal timing delays through each of the circuit blocks;

(c) determining the maximum signal timing delays through the entire circuit network;

(d) calculating a "slack time" value for each of the circuit blocks by subtracting the maximum signal timing delays from the maximum permissible signal timing delays, and allocating "slack time" values to each circuit block according to its respective timing delay;

(e) calculating a "lateness time" value for each of the circuit blocks by summing the "slack times" of the respective circuit blocks with the "slack times" of all circuit blocks in the entire network which contribute to signal delay to the respective block;

(f) incrementing all circuit block power drive levels to their respective next higher levels;

(g) repeating steps (b)-(e) to calculate a new "lateness time" value for each of the circuit blocks at the respective next higher power drive levels;

(h) forming a performance derivative for each circuit block by subtracting the "lateness time" value calculated in step (g) from the "lateness time" value calculated in step (e), and dividing the result by a denominator formed by subtracting the circuit block incremented power drive level from the previous power drive level;

(i) identifying the circuit blocks having the highest performance derivatives and retaining the incremented power drive level for at least one circuit block having the highest performance derivative while returning the remaining circuit blocks to their last previous power drive levels; and

(j) repeating steps (b)-(i) until all "lateness time" values are substantially reduced to zero, and choosing the respective circuit block power drive levels which are used to derive this result, and physically implementing in the LSI circuit network each of the chosen power drive levels in the respective circuit blocks as the operable power drive level for the circuit block.