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Method of optimizing signal timing delays and power consumption in LSI circuits

  • US 4,698,760 A
  • Filed: 06/06/1985
  • Issued: 10/06/1987
  • Est. Priority Date: 06/06/1985
  • Status: Expired due to Fees
First Claim
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1. A method of optimizing signal timing delays and power consumption through multi-path LSI circuit networks constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of selectable power drive levels which determine circuit block signal timing delays, the objective of the method being to reduce an LSI circuit network signal timing delay to less than a predetermined maximum signal timing delay while at the same time achieving the lowest LSI circuit network power consumption consistent therewith, comprising the steps of(a) determining the timing delays and power consumption characteristics of each circuit block for all of the plurality of power drive levels;

  • (b) calculating the timing delays, at a first power drive level, through all of the circuit blocks and determining the circuit network timing delays by summing circuit block timing delays through the multi-path circuit network;

    (c) calculating a "slack time" value for each circuit block by subtracting the circuit network timing delays from the maximum permissible circuit network timing delays, and allocating this difference as a "slack time" value for each circuit block according to its relative timing delay through the multi-path circuit network;

    (d) calculating a "lateness time" value for each of the circuit blocks by summing the circuit block "slack time" values through the multi-path network of circuit blocks which contribute to circuit network timing delays;

    (e) repeating step (b)-(d) at a second power drive level;

    (f) forming a performance derivative for each circuit block by subtracting the second power drive level "lateness time" value from the first power drive level "lateness time" value, and dividing the result by a denominator formed by subtracting the second power drive level power consumption from the first power drive level power consumption;

    (g) identifying the circuit blocks having the highest performance derivatives, and setting the power drive level of at least one of such circuit blocks to the second level while returning the remaining circuit blocks to the first power drive level;

    (h) repeating the steps (b)-(g) by substituting the power drive level selected in step (g) for the original first power drive level, and substituting an incrementally increased power drive level for each circuit block for the second power drive level, until all circuit blocks "lateness time" values are reduced to substantially zero; and

    (i) physically implementing in the LSI circuit network the power drive levels of each circuit block as determined from step (h) as the operable power drive levels of each of the circuit blocks.

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