Self repair large scale integrated circuit

• US 4,698,807 A
• Filed: 12/11/1984
• Issued: 10/06/1987
• Est. Priority Date: 04/11/1983
• Status: Expired due to Fees

• Current Assignee: Commonwealth of Australia
• Original Assignee: Commonwealth of Australia
• Inventors: Marwood, Warren, Clarke, Allen P.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Beausoliel, Jr., Robert W.
• Application Number:
  US06/691,191
• Time in Patent Office: 1,029 Days
• Field of Search: 371/7, 371/8, 371/11, 364/200 MS File, 364/900 MS File
• US Class Current: 714/11
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]

Abstract

The method of self repair of large scale integrated circuit modules (LSI or VLSI) in which a series of systolic processing elements (SPE'"'"'s) arranged in rows (V and H) normal to each other, have sequential paths between elements biased so that normally the data being processed follows the vertical and horizontal rows to maintain a selected topography including the steps of establishing the functionality of each SPE, bypassing any unfunctional SPE by directing the data path of any row to a rear SPE in the nest row, and directing the data path from the said near SPE back to the original row to maintain the original topography.

Claims

1. A method of self repair of large scale integrated circuit modules (LSI or VLSI) comprising the steps of:

arranging a set of systolic processing elements, SPE'"'"'s, in rows orthogonal to each other,

forming sequential paths between SPEs biased so that normally a data path of the data being processed follows the rows,

establishing which, among the SPE'"'"'s of a row, are non-functioning SPE'"'"'s by causing each non-functioning SPE to be flagged by the SPE itself as a result of a comparison of a reference value with an SPE result,

bypassing any such non-functonal SPE by directing the data path from such SPE by triggering diversion of the data to a near SPE in another row, and

directing the data path from said near SPE back toward the original row to establish and maintain the desired path betwee functional SPE'"'"'s.

2. The method of claim 1 in which the circuit has rows of initially redundant SPE'"'"'s to increase the number of replacement SPE'"'"'S available for a selected number of usable rows.

3. The method of claim 1 in which the circuit includes edge rows along edges thereof, and a busy signal is entered into SPE'"'"'s in any edge row to divert the data along the edge row and to indicate non-functioning of an SPE in the edge row.

4. A self repair large scale integrated circuit module comprising:

a set of systolic processing elements or SPE'"'"'s, arranged as arrays of rows orthogonal to each other and in which sequential paths are formed between SPE'"'"'s, and are biased so that normally the data being processed follows the rows to maintain a data path along selected rows,

means for detecting non-functional SPE'"'"'s of each row and for flagging the non-functioning SPE'"'"'s, and

rearrangement means, for detecting at least one non-functoning SPE in a selected row and diverting the data path around the non-functioning SPE by diverting the data path to a functional SPE in another row and back toward a next SPE in said selected row to establish and maintain the desired interconnection path between functional SPE'"'"'s.

6. A self repair large scale circuit module such as an LSI or a VLSI comprising:

a series of systolic processing elements, SPE'"'"'s, arranged in arrays of rows orthogonal to each other, paths between elements biased so that normally the data being processed follows the rows to maintain a selected topography,

at least an extra row of SPE'"'"'s having a dimensional path connecting the extra SPE'"'"'s to each other and to the SPE'"'"'s of other rows,

means, coupled to the SPE'"'"'s, to inject a test signal which detects a non-functional SPE in a selected row and flags the non-functioning SPE,

each SPE including means for diverting said path around the said non-functioning SPE through an SPE in another row,

said diversion being effected from a first functional SPE adjacent said nonfunctioning SPE, to a second functional SPE adjacent the non-functional SPE and on an opposite side thereof compared with said first functional SPE to maintain the originl row path.

5. A self repair large scale integrated circuit module according to claim 7 in which the said large scale integrated circuit has at least a redundant row of SPE'"'"'s to increase the number of SPE'"'"'s available for replacement of non-functional SPE'"'"'s.

7. A self repair large scale integrated circuit module according to claim 6 in which the series includes edge rows along edges thereof, and further comprising means at the edge rows of SPE'"'"'s to initiate a busy operator signal and direct the data path along a side edge row.

8. The method of self repair of large scale integrated circuit modules comprising the steps of:

arranging a set of systolic processing elements in rows orthogonal to each other,

forming sequential paths between elements, biased so that normally the data being processed follows the rows,

establishing non-functioning SPE'"'"'s of each row by causing each non-functioning SPE to be flagged by the SPE itself, as a result of a comparison of a reference value with an SPE result,

bypassing any such non-functional SPE by causing a non-functioning SPE in a first row, to direct the data path from the non-functioning SPE by triggering diversion of the data to a receiving SPE in at least a next row adjacent to the non-functioning SPE, and

directing the data path from said receiving SPE back to an SPE in said first row where functional SPE'"'"'s allow this to establish and maintain, where possible, exit paths from said module in relation to entry paths from said module.

9. A self repair large scale integrated circuit module (LSI or VLSI) comprising:

a set of systolic processing elements (SPE'"'"'s) arranged in rows orthogonal to each other,

a plurality of data transmission paths between elements,

means for selecting the data transmission paths so that data being processed will normally follow the rows,

means, in each SPE, for flagging non-functioning SPE'"'"'s of each row as a result of a comparison of a reference value with an SPE result,

said data transmission paths being biased so that any such non-functioning SPE in a first row directs the data paths from the non-functioning SPE to trigger diversion of the data to a receiving SPE in at least a next row adjacent to the non-functioning SPE, and

means to direct the data path from said receiving SPE back to an SPE in said first row where functional SPE'"'"'s allow this to establish and maintain, where possible, the exit paths in relation to the entry paths.