Method for detecting intermittent error in volatile memory

• US 4,698,808 A
• Filed: 12/05/1985
• Issued: 10/06/1987
• Est. Priority Date: 12/14/1984
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ishii, Takashi
• Primary Examiner(s): Fleming, Michael R.
• Application Number:
  US06/806,076
• Time in Patent Office: 670 Days
• Field of Search: 371/53, 371/54, 371/21, 371/66, 371/63, 371/67, 365/202, 364/200, 364/900
• US Class Current: 714/722
• CPC Class Codes: G06F 11/0763 by bit configuration check, e.g. of formats or tags
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/40 using compression techniques
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Primary and secondary data save areas are established in a volatile memory (CMOS) which is backed up with a battery. The same predetermined data are stored in the primary and secondary data areas together with check sum. At a power on time, the data of the primary area are added together and the data of the secondary area are added together. When both of results of the addition are equal to the check sum, no error is detected. When only one of results of addition is different from the check sum, an intermittent error is detected. When both of results of addition are different from the check sum, battery exhausted condition is detected. If the intermittent error is detected, data of one area whose result of addition is equal to the check sum are copied to other area whose result addition is different from the check sum.

Claims

1. A method for checking data loss in a battery backed volatile memory to distinguish between geometrically uniform data loss resulting from power decay throughout said memory and geometrically random data loss resulting from another cause, comprising the steps of,

processing data stored in two separate save areas in said volatile memory to determine whether the data in one said area is correct, and the data in the other said area incorrect or whether the data in both of said areas is incorrect,

whereby an isolated malfunction, signified by said incorrect data in one but not both of said areas can be distinguished from a permanent error due to discharge of said battery, and

recovering from said data loss by copying said correct data into said area containing said incorrect data.

2. A method for detecting an intermittent error in a volatile memory in which information to be stored is maintained with an auxiliary battery during electric power failure comprising the steps of,

(A) establishing primary and secondary save areas, each of which includes a first and a second storage area in said memory save areas;

(B) writing the same data in said first storage area into each of said primary and secondary data save areas together with check data resulting from processing said data in accordance with a predetermined rule;

(C) reading the output data from said first storage area into said primary and secondary data save areas;

(D) processing data read out of said first storage area into said primary save area in accordance with said predetermined rule to obtain a first data configuration;

(E) processing data read out of said first storage area into said secondary save area in accordance with said predetermined rule to obtain a second data configuration;

(F) reading said check data stored in said second storage area into said primary and secondary data save areas;

(G) comparing said check data from said second storage area in said primary save area with said first data configuration;

wherein an intermittent error is detected when only one of said comparing steps reveals no matching.

3. A method according to claim 2, wherein said step (B) includes the further steps of:

(I) writing the same data in said first storage area into each of said primary and secondary save areas;

(J) obtaining said check data by processing said predetermined data stored in said first storage area in accordance with said predetermined rule; and

(K) writing said check data in said second storage areas into said primary and secondary save areas.

4. A method according to claim 2 wherein said step (B) includes the further step of:

(L) writing said same data into said first storage area of said prrmary data save area;

(M) obtaining said check data by processing said data stored in said first storage area;

(N) writing said check data in said second storage area of said primary save area; and

(O) writing said predetermined data and said check data stored in said first and second storage area of said primary save area into said first and second storage area of said secondary save area respectively.

5. A method according to claim 2, wherein said check data is the sum of said predetermined data.

6. A method according to claim 2, wherein said processing said predetermined data in accordance with a predetermined rule is a predetermined logical operation.

7. A method according to claim 2, wherein said steps (C) through )H) are performed when power is turned on.

8. A method according to claim 2, wherein said steps (C) through (H) are performed when a processor associated with said memory is interrupted.